公开(公告)号：US20130082281A1

公开(公告)日：2013-04-04

申请号：US13249579

申请日：2011-09-30

Applicant: Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

Inventor： Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

IPC: H01L29/16 ,  H01L29/20 ,  H01L27/12 ,  H01L27/092

CPC classification number: H01L21/8258 ,  H01L27/1207

Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

Abstract translation: 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。

公开(公告)号：US4807022A

公开(公告)日：1989-02-21

申请号：US044684

申请日：1987-05-01

Applicant: Thomas E. Kazior ,  Mark S. Durschlag

Inventor： Thomas E. Kazior ,  Mark S. Durschlag

IPC: H01L21/388 ,  H01L21/74 ,  H01L23/36 ,  H01L23/48 ,  H01L23/528 ,  H01L23/34 ,  H01L21/302 ,  H01L27/04

CPC classification number: H01L21/743 ,  H01L21/388 ,  H01L23/36 ,  H01L23/481 ,  H01L23/5283 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/3011

Abstract: A method of simultaneously forming recesses for via holes and tub structures in a substrate is provided in a common etching step by defining a mask pattern for the via hole as a single aperture and by defining a mask pattern for the tub structure as a plurality of thin slots. The slots are chosen to have a smaller cross-sectional dimension than the corresponding dimension for the single aperture. Etchant brought into contact with the substrate will etch the substrate at a slower rate in the slots than in the single apertur such that the via hole will etch completely through the substrate whereas, the tub structure will be etched only partially through the substrate. Conductive material is provided in the tub structure and via hole, and a layer of conductive material is disposed thereover, to provide a heat sink/ ground plane conductor. Electrical contact is provided between the frontside of the substrate and the heat sink/ground plane conductor through the via hole, whereas a low thermal impedance path is provided through the tube structure between a heat dissipating element supported on the frontside of the substrate and the heat sink/ground plane conductor.

Abstract translation: 在通常的蚀刻步骤中，通过将通孔的掩模图案定义为单个孔，并且通过将用于桶结构的掩模图案限定为多个薄的方法，来提供在衬底中同时形成通孔和桶结构的凹槽的方法 插槽 狭槽被选择为具有比单个孔径的相应尺寸更小的横截面尺寸。 与衬底接触的蚀刻剂将在槽中以比单个孔中更慢的速率蚀刻衬底，使得通孔将完全蚀刻通过衬底，而桶结构将仅部分地蚀刻通过衬底。 导电材料设置在桶结构和通孔中，并且在其上设置一层导电材料，以提供散热器/接地面导体。 在基板的前侧和通过通孔的散热器/接地平面导体之间提供电接触，​​而在基板的前侧支撑的散热元件和热量之间通过管结构提供低热阻抗路径 接收/接地平面导体。

公开(公告)号：USRE44303E1

公开(公告)日：2013-06-18

申请号：US13565302

申请日：2012-08-02

Applicant: John Bedinger ,  Michael A. Moore ,  Robert B Hallock ,  Kamal Tabatabaie ,  Thomas E. Kazior

Inventor： John Bedinger ,  Michael A. Moore ,  Robert B Hallock ,  Kamal Tabatabaie ,  Thomas E. Kazior

IPC: H01L21/469 ,  H01L21/31 ,  H01L23/58 ,  H01L21/76

CPC classification number: H01L23/3192 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/4821 ,  H01L23/5221 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract translation: 根据本公开的一个实施例，用于钝化电路器件的方法通常包括提供具有衬底表面的衬底，在衬底表面上形成电子部件，以及用第一保护介电层涂覆衬底表面和电气部件。 第一保护介电层由通常不透水的材料制成，其透湿度小于0.01克/米2 /天，吸湿率小于0.04％，介电常数小于10，介电损耗小于0.005，击穿 电压强度大于800万伏/厘米，电阻率大于1015欧姆厘米，缺陷密度小于0.5 /厘米2。

公开(公告)号：US06175287B1

公开(公告)日：2001-01-16

申请号：US08864533

申请日：1997-05-28

Applicant: James L. Lampen ,  Paul Setzco ,  Thomas E. Kazior ,  Michael G. Kizner ,  John P. Wendler, Jr.

Inventor： James L. Lampen ,  Paul Setzco ,  Thomas E. Kazior ,  Michael G. Kizner ,  John P. Wendler, Jr.

IPC: H01L2302

CPC classification number: H01L23/66 ,  H01L2223/6627 ,  H01L2223/6683 ,  H01L2924/0002 ,  H01L2924/1423 ,  H01L2924/15192 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A plurality of integrated circuits, such as microwave monolithic integrated circuits (MMICs), is supported upon a common carrier substrate having transmission lines for interconnection of signals between terminals of any one of the MMICs and among terminals of the plurality of MMICs. Circuit terminals at the front sides of the respective MMICs are connected electrically by vias to the back sides of the respective MMICs to be adjacent conductive components of the transmission lines. Electrically conductive bumps of metal or epoxy serve to connect the vias to the conductive components of the transmission lines, and to connect also metallized regions of the MMICs to metallized regions of the substrate.

Abstract translation: 诸如微波单片集成电路（MMIC）的多个集成电路被支撑在具有用于互连MMIC中的任一个的终端之间以及多个MMIC的终端之间的信号互连的传输线的公共载体衬底上。 各个MMIC的前侧的电路端子通过通孔与相应的MMIC的背面电连接成与传输线路相邻的导电部件。 金属或环氧树脂的导电凸块用于将通孔连接到传输线的导电部件，并将MMIC的金属化区域连接到衬底的金属化区域。

公开(公告)号：US5343071A

公开(公告)日：1994-08-30

申请号：US54380

申请日：1993-04-28

Applicant: Thomas E. Kazior ,  John C. Huang

Inventor： Thomas E. Kazior ,  John C. Huang

IPC: H01L21/768 ,  H01L23/48 ,  H01L27/06 ,  H01L29/417 ,  H01L29/06

CPC classification number: H01L29/4175 ,  H01L21/76898 ,  H01L23/481 ,  H01L27/0605 ,  H01L2924/0002 ,  H01L2924/10158

Abstract: A semiconductor structure having an active layer formed over a first surface of a substrate. The semiconductor structure includes an electrode formed over a first surface of the structure. A conductive layer is formed over a second surface of the substrate. A conductor section passes through the semiconductor structure between the electrode and the conductive layer. The conductor section includes two conductive elements, one having a first end connected to the electrode and a second end terminating in the semiconductor structure; and the other conductive element having a first end connected to the conductive layer and a second end connected to the second end of the first conductive element. The second end terminates at, or in, an etch resistant layer disposed in the semiconductor structure between the active layer and the substrate. The method for forming the conductive sections includes etching the second via hole from the second surface of the substrate until the etching reaches an etch resistant layer. The walls of the second via hole and exposed portions of the conductive material covering the walls of the first via hole are covered with an electrically conductive material.

Abstract translation: 一种在衬底的第一表面上形成的有源层的半导体结构。 半导体结构包括形成在该结构的第一表面上的电极。 在衬底的第二表面上形成导电层。 导体部分穿过电极和导电层之间的半导体结构。 导体部分包括两个导电元件，一个具有连接到电极的第一端和终止在半导体结构中的第二端; 并且另一导电元件具有连接到导电层的第一端和连接到第一导电元件的第二端的第二端。 第二端终止于设置在有源层和衬底之间的半导体结构中的耐蚀刻层，或其中。 用于形成导电部分的方法包括从衬底的第二表面蚀刻第二通孔，直到蚀刻到达耐蚀刻层。 第二通孔的壁和覆盖第一通孔的壁的导电材料的暴露部分被导电材料覆盖。

公开(公告)号：US4794093A

公开(公告)日：1988-12-27

申请号：US44685

申请日：1987-05-01

Applicant: Elsa K. Tong ,  Thomas E. Kazior

Inventor： Elsa K. Tong ,  Thomas E. Kazior

IPC: H01L21/308 ,  H01L21/74 ,  H01L23/367 ,  H01L23/48 ,  H01L19/00

CPC classification number: H01L21/743 ,  H01L21/308 ,  H01L23/367 ,  H01L23/3677 ,  H01L23/481 ,  H01L2924/0002 ,  H01L2924/10158 ,  H01L2924/10329 ,  Y10S148/026 ,  Y10S148/05 ,  Y10S148/105 ,  Y10S148/135

Abstract: A technique for etching tub structures and vias on the backside of a wafer comprised of gallium arsenide and for providing a planar surface on said backside of the gallium arsenide wafer is described. The tubs are formed by providing a layer of resist over the backside of the gallium arsenide substrate, and this layer is patterned to provide selected areas covering regions where tub structures and vias will be provided. In the selectively exposed regions, palladium and gold are sequentially deposited. The resist pattern is then stripped, and a second resist layer pattern is deposited masking portions of the continuous conductive layer and areas where vias are to be provided. The tub structures are then provided by suitably etching the tub to undercut portions of the resist and the palladium layer. A second continuous conductive coating is then provided in the tub structure to provide a plating layer for subsequent plating of a gold film over the palladium. Preferably, the gold is plated to completely or substantially completely fill the tub. The vias are then provided on the backside of the wafer by masking the first continuous conductive coating and the tub regions and etching the unexposed regions of the substrate to provide the via holes. The via holes are then plated with a continuous conductive layer of palladium and then gold to substantially fill the via.

Abstract translation: 描述了在由砷化镓构成的晶片的背面上蚀刻槽结构和通孔并在砷化镓晶片的所述背面上提供平坦表面的技术。 通过在砷化镓衬底的背面上提供一层抗蚀剂来形成桶体，并且对该层进行图案化，以提供覆盖其中将提供桶结构和通孔的区域的选定区域。 在选择性暴露的区域中，依次沉积钯和金。 然后剥离抗蚀剂图案，并且沉积第二抗蚀剂层图案，掩蔽连续导电层的掩模部分和要设置通孔的区域。 然后通过适当地蚀刻桶以将抗蚀剂和钯层的部分倒下来提供浴缸结构。 然后在桶结构中提供第二连续导电涂层以提供用于随后在钯上镀覆金膜的镀层。 优选地，金被镀以完全或基本上完全填充桶。 然后通过掩蔽第一连续导电涂层和桶区并且蚀刻基板的未曝光区域以提供通孔，将通孔设置在晶片的背面。 然后将通孔用镀钯的连续导电层然后镀金，以基本上填充通孔。

公开(公告)号：US08575666B2

公开(公告)日：2013-11-05

申请号：US13249579

申请日：2011-09-30

Applicant: Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

Inventor： Jeffrey R. LaRoche ,  Thomas E. Kazior ,  William E. Hoke

IPC: H01L31/113

CPC classification number: H01L21/8258 ,  H01L27/1207

Abstract: A semiconductor structure having compound semiconductor (CS) device formed in a compound semiconductor of the structure and an elemental semiconductor device formed in an elemental semiconductor layer of the structure. The structure includes a layer having an elemental semiconductor device is disposed over a buried oxide (BOX) layer. A selective etch layer is disposed between the BOX layer and a layer for a compound semiconductor device. The selective etch layer enables selective etching of the BOX layer to thereby maximize vertical and lateral window etch process control for the compound semiconductor device grown in etched window. The selective etch layer has a lower etch rate than the etch rate of the BOX layer.

Abstract translation: 具有形成在该结构的化合物半导体中的化合物半导体（CS）器件的半导体结构和形成在该结构的元素半导体层中的元素半导体器件。 该结构包括具有元素半导体器件的层设置在掩埋氧化物（BOX）层上。 选择性蚀刻层设置在BOX层和化合物半导体器件的层之间。 选择性蚀刻层能够选择性地蚀刻BOX层，从而最大化在蚀刻窗口中生长的化合物半导体器件的垂直和侧向窗蚀刻工艺控制。 选择性蚀刻层具有比BOX层的蚀刻速率更低的蚀刻速率。

公开(公告)号：US08466555B2

公开(公告)日：2013-06-18

申请号：US13152481

申请日：2011-06-03

Applicant: Ram V. Chelakara ,  Thomas E. Kazior ,  Jeffrey R. LaRoche

Inventor： Ram V. Chelakara ,  Thomas E. Kazior ,  Jeffrey R. LaRoche

IPC: H01L23/48

CPC classification number: H01L29/452 ,  H01L29/2003 ,  H01L29/7787

Abstract: A semiconductor structure is provided having: a semiconductor; a gold-free electrically conductive structure in ohmic contact with the semiconductor; and a pair of electrically conductive layers separated by a layer of silicon. The structure includes: a refractory metal layer disposed in contact with the semiconductor; and wherein one of the pair of electrically conductive layers separated by the layer of silicon is the refractory metal layer. A second layer of silicon is disposed on a second one of the pair of pair of electrically conductive layers and including a third electrically conducive layer on the second layer of silicon. In one embodiment, the semiconductor includes a III-V material.

Abstract translation: 提供一种半导体结构，其具有：半导体; 与半导体欧姆接触的无金导电结构; 以及一层由硅层隔开的导电层。 该结构包括：与半导体接触设置的难熔金属层; 并且其中由所述硅层分离的所述一对导电层中的一个是难熔金属层。 第二层硅层被设置在一对导电层中的第二层上，并且在第二层硅上包括第三导电层。 在一个实施例中，半导体包括III-V材料。

公开(公告)号：US07902083B2

公开(公告)日：2011-03-08

申请号：US12691216

申请日：2010-01-21

Applicant: John M. Bedinger ,  Michael A. Moore ,  Robert B. Hallock ,  Kamal Tabatabaie Alavi ,  Thomas E. Kazior

Inventor： John M. Bedinger ,  Michael A. Moore ,  Robert B. Hallock ,  Kamal Tabatabaie Alavi ,  Thomas E. Kazior

IPC: H01L21/469 ,  H01L21/31 ,  H01L23/58 ,  H01L21/76

CPC classification number: H01L23/3192 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/4821 ,  H01L23/5221 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract translation: 根据本公开的一个实施例，用于钝化电路器件的方法通常包括提供具有衬底表面的衬底，在衬底表面上形成电子部件，以及用第一保护介电层涂覆衬底表面和电气部件。 第一保护介电层由通常不透水的材料制成，其透湿度小于0.01克/米2 /天，吸湿率小于0.04％，介电常数小于10，介电损耗小于0.005，击穿 电压强度大于800万伏/厘米，电阻率大于1015欧姆厘米，缺陷密度小于0.5 /厘米2。

公开(公告)号：US20100120254A1

公开(公告)日：2010-05-13

申请号：US12691216

申请日：2010-01-21

Applicant: John M. Bedinger ,  Michael A. Moore ,  Robert B. Hallock ,  Kamal Tabatabaie Alavi ,  Thomas E. Kazior

Inventor： John M. Bedinger ,  Michael A. Moore ,  Robert B. Hallock ,  Kamal Tabatabaie Alavi ,  Thomas E. Kazior

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L23/3192 ,  H01L21/7682 ,  H01L21/76832 ,  H01L21/76834 ,  H01L23/4821 ,  H01L23/5221 ,  H01L24/48 ,  H01L2224/05599 ,  H01L2224/45014 ,  H01L2224/451 ,  H01L2224/48091 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/85399 ,  H01L2224/8592 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01006 ,  H01L2924/01011 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01015 ,  H01L2924/01019 ,  H01L2924/01023 ,  H01L2924/01031 ,  H01L2924/01032 ,  H01L2924/01033 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01056 ,  H01L2924/01072 ,  H01L2924/01073 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10329 ,  H01L2924/1305 ,  H01L2924/1306 ,  H01L2924/14 ,  H01L2924/1423 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2224/45099

Abstract: According to one embodiment of the disclosure, a method for passivating a circuit device generally includes providing a substrate having a substrate surface, forming an electrical component on the substrate surface, and coating the substrate surface and the electrical component with a first protective dielectric layer. The first protective dielectric layer is made of a generally moisture insoluble material having a moisture permeability less than 0.01 gram/meter2/day, a moisture absorption less than 0.04 percent, a dielectric constant less than 10, a dielectric loss less than 0.005, a breakdown voltage strength greater than 8 million volts/centimeter, a sheet resistivity greater than 1015 ohm-centimeter, and a defect density less than 0.5/centimeter2.

Abstract translation: 根据本公开的一个实施例，用于钝化电路器件的方法通常包括提供具有衬底表面的衬底，在衬底表面上形成电子部件，以及用第一保护介电层涂覆衬底表面和电气部件。 第一保护介电层由通常不透水的材料制成，其透湿度小于0.01克/米2 /天，吸湿率小于0.04％，介电常数小于10，介电损耗小于0.005，击穿 电压强度大于800万伏/厘米，电阻率大于1015欧姆厘米，缺陷密度小于0.5 /厘米2。