SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
    2.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
    用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法

    公开(公告)号:US20090108466A1

    公开(公告)日:2009-04-30

    申请号:US12103765

    申请日:2008-04-16

    IPC分类号: H01L23/48 H01L21/4763

    摘要: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译: 中间层连接(即垂直连接)可以基于硬掩模材料形成,硬掩模材料可以位于层间电介质材料的内部或之上,其中一个横向尺寸由沟槽掩模限定,从而获得所需的中间层 连接在共同的图案化过程中。 此外,金属线的至少某些部分的厚度可以以高度的柔性来调节,从而提供了显着降低金属线中金属线的整体电阻率的可能性,其中器件性能可能显着地取决于电阻率 比寄生电容。

    SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR PATTERNING VERTICAL CONTACTS AND METAL LINES IN A COMMON ETCH PROCESS 有权
    用于在常见蚀刻过程中绘制垂直接触和金属线的半导体器件和方法

    公开(公告)号:US20120220119A1

    公开(公告)日:2012-08-30

    申请号:US13468083

    申请日:2012-05-10

    IPC分类号: H01L21/768 H01L21/308

    摘要: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译: 中间层连接(即垂直连接)可以基于硬掩模材料形成,硬掩模材料可以位于层间电介质材料的内部或之上,其中一个横向尺寸由沟槽掩模限定,从而获得所需的中间层 连接在共同的图案化过程中。 此外,金属线的至少某些部分的厚度可以以高度的柔性来调节,从而提供了显着降低金属线中金属线的整体电阻率的可能性,其中器件性能可能显着地取决于电阻率 比寄生电容。

    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    5.
    发明授权
    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
    在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法

    公开(公告)号:US08741770B2

    公开(公告)日:2014-06-03

    申请号:US13468083

    申请日:2012-05-10

    IPC分类号: H01L23/48 H01L21/4763

    摘要: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译: 中间层连接(即垂直连接)可以基于硬掩模材料形成,硬掩模材料可以位于层间电介质材料的内部或之上,其中一个横向尺寸由沟槽掩模限定,从而获得所需的中间层 连接在共同的图案化过程中。 此外,金属线的至少某些部分的厚度可以以高度的柔性来调节,从而提供了显着降低金属线中金属线的整体电阻率的可能性,其中器件性能可能显着地取决于电阻率 比寄生电容。

    METHOD OF SELECTIVELY FORMING A CONDUCTIVE BARRIER LAYER BY ALD
    6.
    发明申请
    METHOD OF SELECTIVELY FORMING A CONDUCTIVE BARRIER LAYER BY ALD 有权
    通过ALD选择形成导电障碍层的方法

    公开(公告)号:US20080132057A1

    公开(公告)日:2008-06-05

    申请号:US11757022

    申请日:2007-06-01

    IPC分类号: H01L21/4763

    CPC分类号: H01L21/76844

    摘要: By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.

    摘要翻译: 通过在自限制沉积工艺之前或期间提供表面改性方法,可以选择性地改变本身高共形沉积行为,以便在比表面积获得可靠的覆盖,同时显着地减少或抑制不想要的表面积 ,例如高分辨率半导体器件的先进金属化结构中的通孔的底部。

    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process
    7.
    发明授权
    Semiconductor device and method for patterning vertical contacts and metal lines in a common etch process 有权
    在普通蚀刻工艺中用于图案化垂直接触和金属线的半导体器件和方法

    公开(公告)号:US08198190B2

    公开(公告)日:2012-06-12

    申请号:US12103765

    申请日:2008-04-16

    IPC分类号: H01L23/48 H01L21/4763

    摘要: Interlayer connections, i.e., vertical connections, may be formed on the basis of a hard mask material, which may be positioned below, within or above an interlayer dielectric material, wherein one lateral dimension is defined by a trench mask, thereby obtaining a desired interlayer connection in a common patterning process. Furthermore, the thickness of at least certain portions of the metal lines may be adjusted with a high degree of flexibility, thereby providing the possibility of significantly reducing the overall resistivity of metal lines in metal levels, in which device performance may significantly depend on resistivity rather than parasitic capacitance.

    摘要翻译: 中间层连接(即垂直连接)可以基于硬掩模材料形成,硬掩模材料可以位于层间电介质材料的内部或之上,其中一个横向尺寸由沟槽掩模限定,从而获得所需的中间层 连接在共同的图案化过程中。 此外,金属线的至少某些部分的厚度可以以高度的柔性来调节,从而提供了显着降低金属线中金属线的整体电阻率的可能性,其中器件性能可能显着地取决于电阻率 比寄生电容。

    Method of selectively forming a conductive barrier layer by ALD
    8.
    发明授权
    Method of selectively forming a conductive barrier layer by ALD 有权
    通过ALD选择性地形成导电阻挡层的方法

    公开(公告)号:US08173538B2

    公开(公告)日:2012-05-08

    申请号:US11757022

    申请日:2007-06-01

    IPC分类号: H01L21/4763

    CPC分类号: H01L21/76844

    摘要: By providing a surface modification process prior to or during a self-limiting deposition process, the per se highly conformal deposition behavior may be selectively changed so as to obtain reliable coverage at specific surface areas, while significantly reducing or suppressing a deposition above unwanted surface areas, such as the bottom of a via in advanced metallization structures of highly scaled semiconductor devices.

    摘要翻译: 通过在自限制沉积工艺之前或期间提供表面改性方法,可以选择性地改变本身高共形沉积行为,以便在比表面积获得可靠的覆盖,同时显着地减少或抑制不想要的表面积 ,例如高分辨率半导体器件的先进金属化结构中的通孔的底部。