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    Memory latency compensation
    2.
    发明授权
    Memory latency compensation 有权
    内存延迟补偿

    公开(公告)号：US06351793B2

    公开(公告)日：2002-02-26

    申请号：US09137439

    申请日：1998-08-20

    申请人： Thomas Henkel

    发明人： Thomas Henkel

    IPC分类号： G06F1200

    CPC分类号： G06F5/16 ,  G01R31/31919 ,  G01R31/31921 ,  G06F5/06

    摘要： An impact of a memory latency time on repeat operations with a memory is reduced by providing a repeat start buffer for buffering a beginning of a data sequence to be repeatedly accessed, and a repeat switching unit, connected with the memory and the repeat start buffer, for switching therebetween for accessing the buffered beginning of the data sequence to be repeatedly accessed when the data sequence is to be repeated. In case of jump operations, a further reduction is achieved by providing a first and a second data buffer connectable with the memory for buffering data sequences, and a switching unit, connected with the data buffers for switching therebetween. The memory is accessible for each data buffer during an idle memory accessing time of the other data buffer for buffering a beginning of a data sequence to be accessed successively.

    摘要翻译： 通过提供用于缓冲重复访问的数据序列的开始的重复启动缓冲器以及与存储器和重复启动缓冲器连接的重复切换单元，减少了存储器等待时间对具有存储器的重复操作的影响， 用于在数据序列要被重复时在其间切换用于访问要重复访问的数据序列的缓冲开始。 在跳跃操作的情况下，通过提供与存储器可连接的用于缓冲数据序列的第一和第二数据缓冲器以及与数据缓冲器连接以在其间切换的切换单元来实现进一步的减少。 在另一数据缓冲器的空闲存储器访问时间期间，每个数据缓冲器可访问存储器，用于缓冲要连续访问的数据序列的开始。

    METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST
    4.
    发明申请
    METHOD AND APPARATUS FOR TESTING A DEVICE-UNDER-TEST 有权
    用于测试设备下测试的方法和装置

    公开(公告)号：US20130193993A1

    公开(公告)日：2013-08-01

    申请号：US13574573

    申请日：2010-01-20

    申请人： Gil Golov ,  Thomas Henkel ,  Ronald Larson ,  Ulrich Knoch

    发明人： Gil Golov ,  Thomas Henkel ,  Ronald Larson ,  Ulrich Knoch

    IPC分类号： G01R31/319

    CPC分类号： G01R31/319 ,  G01R31/31907

    摘要： A method for testing a device-under-test includes receiving, from at least one test channel circuit dedicated to communicate with an input/output pin of the device-under-test by means of at least one hardware resource, at least one logical control command describing a desired operation of the at least one hardware resource, and converting, by means of a resource controller, the at least one logical control command into at least one dedicated control command for the at least one hardware resource, wherein the at least one dedicated control command is adapted to be received by a physical implementation of the at least one hardware resource.

    摘要翻译： 一种用于测试被测器件的方法包括：从至少一个测试通道电路接收至少一个逻辑控制器，所述至少一个测试通道电路专用于通过至少一个硬件资源与待测器件的输入/输出引脚通信; 描述所述至少一个硬件资源的期望操作，以及通过资源控制器将所述至少一个逻辑控制命令转换成所述至少一个硬件资源的至少一个专用控制命令，其中所述至少一个 专用控制命令适于由所述至少一个硬件资源的物理实现来接收。

    Channel with domain crossing
    6.
    发明申请
    Channel with domain crossing 有权
    频道与域交叉

    公开(公告)号：US20050069030A1

    公开(公告)日：2005-03-31

    申请号：US10917966

    申请日：2004-08-13

    申请人： Thomas Henkel

    发明人： Thomas Henkel

    IPC分类号： G01R31/28 ,  G01R31/317 ,  H04B3/46

    CPC分类号： G01R31/31727

    摘要： A channel adapted for at least one of providing and receiving signals includes a channel clock domain, whereby said channel clock domain is under clock control of a channel clock. The channel clock domain includes at least one of: a drive path adapted for providing signals and a receive path adapted for receiving signals. The channel also includes a service clock domain adapted for at least one of providing data to and receiving data from said channel clock domain, whereby said service clock domain is under clock control of a service clock.

    摘要翻译： 适于提供和接收信号中的至少一个信道的信道包括信道时钟域，由此所述信道时钟域在信道时钟的时钟控制之下。 信道时钟域包括以下中的至少一个：适于提供信号的驱动路径和适于接收信号的接收路径。 信道还包括业务时钟域，适用于向所述信道时钟域提供数据和从所述信道时钟域接收数据中的至少一个，由此所述业务时钟域在服务时钟的时钟控制之下。

    Inhibitors of fatty acid oxidation for prophylaxis and treatment of diseases related to mitochondrial dysfunction
    7.
    发明申请
    Inhibitors of fatty acid oxidation for prophylaxis and treatment of diseases related to mitochondrial dysfunction 审中-公开
    抑制脂肪酸氧化预防和治疗与线粒体功能障碍有关的疾病

    公开(公告)号：US20050004173A1

    公开(公告)日：2005-01-06

    申请号：US10832801

    申请日：2004-04-26

    申请人： Thomas Henkel ,  Christoph Rehfuess

    发明人： Thomas Henkel ,  Christoph Rehfuess

    IPC分类号： A61K31/336 ,  A61K31/4025 ,  A61K31/435 ,  A61K31/443 ,  A61K31/495

    CPC分类号： A61K31/336 ,  A61K31/4025 ,  A61K31/435 ,  A61K31/443 ,  A61K31/495

    摘要： Described are a method and a composition for preventing and/or treating a disease related to mitochondrial dysfunction by inhibiting the fatty acid oxidation of one or more cells of an organism. Particularly, the fatty acid oxidation is inhibited by inhibiting the expression and/or activity of the enzyme Carnitin-Palmitoyl-Transferase-1 (CPT-1) by means of an arylalkyl- or arlyoxyalkyl-substitued oxirane carboxylic acid or pharmaceutically acceptable salts and derivatives of the arylalkyl-substituted oxirane carboxylic acid.

    摘要翻译： 描述了通过抑制生物体的一个或多个细胞的脂肪酸氧化来预防和/或治疗与线粒体功能障碍有关的疾病的方法和组合物。 特别地，通过芳基烷基 - 或芳氧基烷基取代的环氧乙烷羧酸或其药学上可接受的盐和衍生物抑制肉碱 - 棕榈酰转移酶-1（CPT-1）的表达和/或活性来抑制脂肪酸氧化 的芳基烷基取代的环氧乙烷羧酸。

    Multi-channel architecture with channel independent clock signals
    8.
    发明授权
    Multi-channel architecture with channel independent clock signals 失效
    具有通道独立时钟信号的多通道架构

    公开(公告)号：US6055644A

    公开(公告)日：2000-04-25

    申请号：US50289

    申请日：1998-03-30

    申请人： Thomas Henkel

    发明人： Thomas Henkel

    IPC分类号： G01R31/3183 ,  G01R31/319 ,  G06F1/06 ,  G06F1/04

    CPC分类号： G06F1/06 ,  G01R31/31922

    摘要： Described is a multi-channel architecture comprising a central master clock generator for generating a central master clock signal and a plurality of channels connectable with inputs or outputs of a device. The multi-channel architecture further includes a channel master clock gate assigned to a respective channel of the plurality of channels, for receiving the central master clock signal and for generating a channel clock signal from the central master clock signal. The multi-channel architecture can be used in a tester arrangement, and preferably in an IC tester. The described multi-channel architecture allows clock signals to be provided for each one of the channels independent of other channels, e.g. to apply a continuous clock signal in one channel while the clock signal in other channels might be changed, e.g. in order to receive new timing edges as references for testing a DUT.

    摘要翻译： 描述了一种多通道架构，其包括用于产生中央主时钟信号的中央主时钟发生器和可与设备的输入或输出连接的多个通道。 多通道架构还包括分配给多个通道中的相应通道的通道主时钟门，用于接收中央主时钟信号并用于从中央主时钟信号产生通道时钟信号。 多通道架构可以用于测试器布置，并且优选地在IC测试器中使用。 所描述的多通道架构允许为独立于其他通道的每个通道提供时钟信号，例如。 以在一个通道中施加连续的时钟信号，而其它通道中的时钟信号可能被改变，例如， 以便接收新的时序边缘作为测试DUT的参考。

    Transfer clocks for a multi-channel architecture
    9.
    发明授权
    Transfer clocks for a multi-channel architecture 有权
    传输多通道架构时钟

    公开(公告)号：US08170164B2

    公开(公告)日：2012-05-01

    申请号：US10830341

    申请日：2004-04-22

    申请人： Thomas Henkel ,  Ralf Killig

    发明人： Thomas Henkel ,  Ralf Killig

    IPC分类号： H04L7/00

    CPC分类号： G01R31/31922 ,  G06F1/10

    摘要： A multi-channel architecture comprising a central facility that is under clock control of a central facility's clock signal, and a central transfer clock generator adapted for deriving a central transfer clock signal from the central facility's clock signal. The multi-channel architecture further comprises a set of n channels, with n being a natural number, wherein each channel is under clock control of one out of a plurality of clock signals. Each of the channels comprises a channel transfer clock generator adapted for deriving a channel transfer clock signal from a clock signal of the respective channel, wherein the central facility's clock signal and the clock signals of the channels comprise at least two different clock signals. The transfer clock period of the central transfer clock signal is substantially equal to each of the transfer clock periods of the channel transfer clock signals.

    摘要翻译： 一种多通道架构，包括中央设备的时钟信号的时钟控制的中央设备和适于从中央设施的时钟信号导出中央传送时钟信号的中央传送时钟发生器。 多通道架构还包括一组n个通道，其中n是自然数，其中每个通道处于多个时钟信号中的一个的时钟控制之下。 每个信道包括适于从相应信道的时钟信号导出信道传输时钟信号的信道传输时钟发生器，其中中心设备的时钟信号和信道的时钟信号包括至少两个不同的时钟信号。 中央传送时钟信号的传送时钟周期基本上等于信道传输时钟信号的每个传送时钟周期。

    Channel with domain crossing
    10.
    发明授权
    Channel with domain crossing 有权
    频道与域交叉

    公开(公告)号：US07346102B2

    公开(公告)日：2008-03-18

    申请号：US10917966

    申请日：2004-08-13

    申请人： Thomas Henkel

    发明人： Thomas Henkel

    IPC分类号： H04B3/46

    CPC分类号： G01R31/31727

    摘要： A channel adapted for at least one of providing and receiving signals comprises a channel clock domain, whereby said channel clock domain is under clock control of a channel clock. The channel clock domain comprises at least one of: a drive path adapted for providing signals and a receive path adapted for receiving signals. The channel further comprises a service clock domain adapted for at least one of providing data to and receiving data from said channel clock domain, whereby said service clock domain is under clock control of a service clock.

    摘要翻译： 适于提供和接收信号中的至少一个的信道包括信道时钟域，由此所述信道时钟域在信道时钟的时钟控制之下。 通道时钟域包括以下至少之一：适于提供信号的驱动路径和适于接收信号的接收路径。 该信道还包括业务时钟域，适用于向所述信道时钟域提供数据和接收数据中的至少一个，由此所述业务时钟域在服务时钟的时钟控制之下。