公开(公告)号：US20070018745A1

公开(公告)日：2007-01-25

申请号：US11186059

申请日：2005-07-21

申请人： Thomas Knotts ,  Gunter Steinbach

发明人： Thomas Knotts ,  Gunter Steinbach

IPC分类号： H03B5/12

CPC分类号： H03L7/113 ,  H03L7/087 ,  H03L7/0891

摘要： A technique for establishing a tuning signal window for a multi-band VCO involves setting the tuning signal window to an initial size, preferably a relatively small size, and determining whether the VCO is churning. When the VCO is determined to be churning, the tuning signal window is expanded until the VCO stops churning. In an embodiment, the tuning signal window is expanded incrementally until the tuning signal window is large enough to include a solution, where a solution is defined as an operating point along a frequency band that satisfies both the setpoint frequency and tuning window signal requirements. The tuning signal window can be set at an offset relative to the tuning signal zero to compensate for shifts in the frequency bands that may result from changes in operating conditions.

摘要翻译： 用于建立多频带VCO的调谐信号窗口的技术包括将调谐信号窗口设置为初始尺寸，优选地相对较小的尺寸，以及确定VCO是否正在搅拌。 当VCO被确定为搅拌时，调谐信号窗口被扩展直到VCO停止搅动。 在一个实施例中，调谐信号窗口被递增地扩展，直到调谐信号窗口足够大以包括解，其中解被定义为沿着满足设定点频率和调谐窗口信号要求的频带的操作点。 调谐信号窗口可以设置为相对于调谐信号零的偏移量，以补偿由于工作条件变化而导致的频带中的偏移。

公开(公告)号：US20060139108A1

公开(公告)日：2006-06-29

申请号：US11356514

申请日：2006-02-17

申请人： Gunter Steinbach ,  Brian Galloway ,  Thomas Knotts

发明人： Gunter Steinbach ,  Brian Galloway ,  Thomas Knotts

IPC分类号： H03L7/00

CPC分类号： H03L7/113 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L7/14 ,  H04L7/0083 ,  H04L7/033

摘要： The frequency changes in a bang-bang PLL that are generated using a digital phase detector's up/down signal are initially set to produce a faster pull-in rate and then reduced to produce a slower pull-in rate. The faster pull-in involves relatively large frequency changes and the slower pull-in rate involves smaller frequency changes. The changes in frequency of a bang-bang PLL can be implemented using a step size controller that includes timing control logic and step size logic. The function of the timing control logic is to control the timing of step size changes. The function of the step size logic is to set the step size of the frequency changes that are made by the VCO in response to the pd_up/down signal that is delivered directly to the VCO from the digital phase detector.

摘要翻译： 初始设置使用数字相位检测器的上/下信号产生的爆炸PLL中的频率变化，以产生更快的拉入速率，然后减小以产生较慢的拉入速率。 更快的引入涉及相对较大的频率变化，较慢的引入速率涉及较小的频率变化。 可以使用包括定时控制逻辑和步长逻辑的步长控制器来实现爆炸PLL的频率变化。 定时控制逻辑的功能是控制步长变化的时序。 步长逻辑的功能是响应于从数字相位检测器直接传送到VCO的pd_up / down信号来设置由VCO产生的频率变化的步长。

公开(公告)号：US20050200391A1

公开(公告)日：2005-09-15

申请号：US10797964

申请日：2004-03-11

申请人： Gunter Steinbach ,  Brian Galloway ,  Thomas Knotts

发明人： Gunter Steinbach ,  Brian Galloway ,  Thomas Knotts

IPC分类号： H03L7/00

CPC分类号： H03L7/113 ,  H03L7/087 ,  H03L7/0891 ,  H03L7/095 ,  H03L7/099 ,  H03L7/107 ,  H03L7/14 ,  H04L7/0083 ,  H04L7/033

摘要： The frequency changes in a bang-bang PLL that are generated using a digital phase detector's up/down signal are initially set to produce a faster pull-in rate and then reduced to produce a slower pull-in rate. The faster pull-in involves relatively large frequency changes and the slower pull-in rate involves smaller frequency changes. The changes in frequency of a bang-bang PLL can be implemented using a step size controller that includes timing control logic and step size logic. The function of the timing control logic is to control the timing of step size changes. The function of the step size logic is to set the step size of the frequency changes that are made by the VCO in response to the pd_up/down signal that is delivered directly to the VCO from the digital phase detector.

摘要翻译： 初始设置使用数字相位检测器的上/下信号产生的爆炸PLL中的频率变化，以产生更快的拉入速率，然后减小以产生较慢的拉入速率。 更快的引入涉及相对较大的频率变化，较慢的引入速率涉及较小的频率变化。 可以使用包括定时控制逻辑和步长逻辑的步长控制器来实现爆炸PLL的频率变化。 定时控制逻辑的功能是控制步长变化的时序。 步长逻辑的功能是响应于从数字相位检测器直接传送到VCO的pd_up / down信号来设置由VCO产生的频率变化的步长。

公开(公告)号：US20060082402A1

公开(公告)日：2006-04-20

申请号：US10967824

申请日：2004-10-18

申请人： Thomas Knotts

发明人： Thomas Knotts

IPC分类号： H03L7/06

CPC分类号： H03L7/091 ,  H03L7/087 ,  H03L7/10 ,  H04L7/033

摘要： A technique for reducing the likelihood that a frequency detector will incorrectly assert control over a VCO because of metastable-induced errors involves qualifying frequency detector control signals by requiring multiple consecutive control signals that indicate the frequency detector should assert control over the VCO before the frequency detector is allowed to assert control over the VCO. In an embodiment, the frequency detector control signals are qualified by a series of full-swing library cell flip-flops.

公开(公告)号：US20050174185A1

公开(公告)日：2005-08-11

申请号：US10775960

申请日：2004-02-10

申请人： Guntor Steinbach ,  Thomas Knotts

发明人： Guntor Steinbach ,  Thomas Knotts

IPC分类号： H03J7/04 ,  H03J7/06 ,  H03J7/28 ,  H03L7/087 ,  H03L7/095 ,  H03L7/10 ,  H04B1/16 ,  H03B1/00

CPC分类号： H03L7/095 ,  H03L7/087 ,  H03L7/10

摘要： Centering a multi-band VCO involves comparing a VCO tuning signal to a pre-established tuning signal window to determine whether to change the frequency band of the multi-band VCO. The frequency band of the multi-band VCO can be changed only when the tuning signal is outside the tuning signal window. Further, the frequency band can be changed as long as the VCO is being controlled by a frequency detector. Once the multi-band VCO achieves lock, the multi-band VCO is changed by at least one more frequency band as long as the VCO tuning signal is still outside the tuning signal window.

摘要翻译： 以多频带VCO为中心包括将VCO调谐信号与预先建立的调谐信号窗口进行比较，以确定是否改变多频带VCO的频带。 只有当调谐信号在调谐信号窗口之外时，才能改变多频带VCO的频带。 此外，只要VCO由频率检测器控制，就可以改变频带。 一旦多频带VCO实现锁定，只要VCO调谐信号仍然在调谐信号窗口之外，多频带VCO就被改变至少一个频带。

公开(公告)号：US20050168430A1

公开(公告)日：2005-08-04

申请号：US10771738

申请日：2004-02-04

申请人： Ken Nishimura ,  Charles Hoke ,  Thomas Knotts

发明人： Ken Nishimura ,  Charles Hoke ,  Thomas Knotts

IPC分类号： G09G3/36

CPC分类号： G09G3/3611 ,  G09G2310/06 ,  G09G2320/0204

摘要： Display contrast in electro-optical display devices is improved using a drive circuit including pixel drive circuits and a common drive circuit. The pixel drive circuits are connected to pixel electrodes of the display device, and are operable to generate respective pixel drive signals that alternate between a first high voltage and a first low voltage differing in voltage by less than or equal to a process-limited maximum. The common drive circuit is connected to a common electrode of the display device, and is operable to generate a common drive signal alternating between a second high voltage and a second low voltage differing in voltage by more than the process-limited maximum. The common drive signal is asymmetrically bipolar with respect to the first low voltage of the pixel drive signal.

摘要翻译： 使用包括像素驱动电路和公共驱动电路的驱动电路来改善电光显示装置中的显示对比度。 像素驱动电路连接到显示装置的像素电极，并且可操作以产生在不同于处理限制最大值的电压不同的第一高电压和第一低电压之间交替的各个像素驱动信号。 公共驱动电路连接到显示装置的公共电极，并且可操作以产生在不同于处理限制最大值的电压不同的第二高电压和第二低电压之间交替的公共驱动信号。 公共驱动信号相对于像素驱动信号的第一低电压是非对称的。

公开(公告)号：US20050105660A1

公开(公告)日：2005-05-19

申请号：US10714037

申请日：2003-11-14

申请人： Thomas Knotts

发明人： Thomas Knotts

IPC分类号： H03D13/00 ,  H03L7/087 ,  H03L7/089 ,  H03L7/113 ,  H03D3/24

CPC分类号： H03L7/0891 ,  H03D13/004 ,  H03L7/087 ,  H03L7/113

摘要： A frequency detector for use with a PLL utilizes a counter and a preset value to produce frequency information related to a VCO signal. The frequency information is used to control the frequency of the VCO signal and to determine whether the VCO signal should be controlled by the frequency detector or a phase detector. Using the counter and preset value involves establishing a preset value that is used to obtain the desired frequency information. The preset value is set such that the counter is at one-half full-scale at the end of a known time period when the VCO signal is oscillating at a target frequency. When the preset value is set to such a value, the most significant bit of the counter after the known time period indicates whether the frequency of the VCO signal is above or below the target frequency.

摘要翻译： 与PLL一起使用的频率检测器利用计数器和预设值来产生与VCO信号相关的频率信息。 频率信息用于控制VCO信号的频率，并确定VCO信号是否应由频率检测器或相位检测器控制。 使用计数器和预设值包括建立用于获得所需频率信息的预设值。 将该预设值设定为使得当VCO信号以目标频率振荡时，计数器在已知时间周期结束时为半满量程。 当预设值被设置为这样的值时，在已知时间段之后的计数器的最高有效位指示VCO信号的频率是高于还是低于目标频率。