公开(公告)号：US08962434B2

公开(公告)日：2015-02-24

申请号：US13545224

申请日：2012-07-10

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

IPC: H01L21/336

CPC classification number: H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28008 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

Abstract translation: 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。

公开(公告)号：US08828831B2

公开(公告)日：2014-09-09

申请号：US13355691

申请日：2012-01-23

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/772 ,  H01L29/417 ,  H01L21/8238

CPC classification number: H01L29/0603 ,  H01L21/8238 ,  H01L21/823807 ,  H01L21/823814 ,  H01L21/84 ,  H01L27/092 ,  H01L29/165 ,  H01L29/41725 ,  H01L29/66628 ,  H01L29/772 ,  H01L29/78

Abstract: Disclosed is a semiconductor article which includes a semiconductor substrate; a gate structure having a spacer adjacent to a conducting material of the gate structure wherein a corner of the spacer is faceted to create a faceted space between the faceted spacer and the semiconductor substrate; and a raised source/drain adjacent to the gate structure, the raised source/drain filling the faceted space and having a surface parallel to the semiconductor substrate. Also disclosed is a method of making the semiconductor article.

Abstract translation: 公开了一种半导体制品，其包括半导体衬底; 栅极结构具有与栅极结构的导电材料相邻的间隔物，其中间隔物的角被刻面以在刻面间隔物和半导体衬底之间产生刻面空间; 以及与栅极结构相邻的升高的源极/漏极，所述升高的源极/漏极填充所述刻面空间并具有平行于所述半导体衬底的表面。 还公开了制造半导体制品的方法。

公开(公告)号：US08759200B2

公开(公告)日：2014-06-24

申请号：US13135031

申请日：2011-06-23

Applicant: Terry Arthur Francis ,  Satoshi Hasaka ,  Paul David Brabant ,  Robert Torres, Jr. ,  Hong He ,  Alexander Reznicek ,  Thomas N. Adam ,  Devendra K. Sadana

Inventor： Terry Arthur Francis ,  Satoshi Hasaka ,  Paul David Brabant ,  Robert Torres, Jr. ,  Hong He ,  Alexander Reznicek ,  Thomas N. Adam ,  Devendra K. Sadana

IPC: H01L21/205

CPC classification number: H01L21/02532 ,  C23C16/30 ,  C23C16/325 ,  C30B25/02 ,  C30B29/06 ,  H01L21/0237 ,  H01L21/02529 ,  H01L21/02573 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/0262 ,  H01L21/02636

Abstract: The present invention discloses that under modified chemical vapor deposition (mCVD) conditions an epitaxial silicon film may be formed by exposing a substrate contained within a chamber to a relatively high carrier gas flow rate in combination with a relatively low silicon precursor flow rate at a temperature of less than about 550° C. and a pressure in the range of about 10 mTorr-200 Torr. Furthermore, the crystalline Si may be in situ doped to contain relatively high levels of substitutional carbon by carrying out the deposition at a relatively high flow rate using tetrasilane as a silicon source and a carbon-containing gas such as dodecalmethylcyclohexasilane or tetramethyldisilane under modified CVD conditions.

Abstract translation: 本发明公开了在改进的化学气相沉积（mCVD）条件下，外延硅膜可以通过将包含在腔室内的衬底暴露于相对高的载气流量与在较低的硅前体流速 小于约550℃，压力范围为约10mTorr-200Torr。 此外，通过在改进的CVD条件下使用四硅烷作为硅源和含碳气体如十二烷基甲基环己硅烷或四甲基二硅烷以相对高的流速进行沉积，可以将晶体Si原位掺杂以含有相对高水平的取代碳 。

公开(公告)号：US08674447B2

公开(公告)日：2014-03-18

申请号：US13457980

申请日：2012-04-27

Applicant: Thomas N Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Thomas N Adam ,  Kangguo Cheng ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L29/78

CPC classification number: H01L21/02609 ,  H01L21/265 ,  H01L21/28026 ,  H01L21/30608 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/3086 ,  H01L29/165 ,  H01L29/66431 ,  H01L29/6653 ,  H01L29/66575 ,  H01L29/66636 ,  H01L29/7848

Abstract: A method and structure of an embedded stressor in a semiconductor transistor device having a sigma-shaped channel sidewall and a vertical isolation sidewall. The embedded stressor structure is made by a first etch to form a recess in a substrate having a gate and first and second spacers. The second spacers are removed and a second etch creates a step in the recess on a channel sidewall. An anisotropic etch creates facets in the channel sidewall of the recess. Where the facets meet, a vertex is formed. The depth of the vertex is determined by the second etch depth (step depth). The lateral position of the vertex is determined by the thickness of the first spacers. A semiconductor material having a different lattice spacing than the substrate is formed in the recess to achieve the embedded stressor structure.

Abstract translation: 具有西格玛通道侧壁和垂直隔离侧壁的半导体晶体管器件中的嵌入式应力源的方法和结构。 嵌入的应力器结构由第一蚀刻制成，以在具有栅极和第一和第二间隔物的衬底中形成凹陷。 去除第二间隔物，并且第二蚀刻在通道侧壁上的凹部中形成台阶。 各向异性蚀刻在凹槽的通道侧壁中产生刻面。 小面相遇时，形成顶点。 顶点的深度由第二蚀刻深度（阶梯深度）决定。 顶点的横向位置由第一间隔件的厚度决定。 在凹部中形成具有与衬底不同的晶格间距的半导体材料，以实现嵌入的应力器结构。

公开(公告)号：US20140024181A1

公开(公告)日：2014-01-23

申请号：US13551054

申请日：2012-07-17

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Bala S. Haran ,  Pranita Kulkarni ,  Amlan Majumdar ,  Stefan Schmitz

IPC: H01L21/8238

CPC classification number: H01L21/84 ,  H01L27/1203

Abstract: A method of forming a semiconductor structure which includes an extremely thin silicon-on-insulator (ETSOI) semiconductor structure having a PFET portion and an NFET portion, a gate structure in the PFET portion and the NFET portion, a high quality nitride spacer adjacent to the gate structures in the PFET portion and the NFET portion and a doped faceted epitaxial silicon germanium raised source/drain (RSD) in the PFET portion. An amorphous silicon layer is formed on the RSD in the PFET portion. A faceted epitaxial silicon RSD is formed on the ETSOI adjacent to the high quality nitride in the NFET portion. The amorphous layer in the PFET portion prevents epitaxial growth in the PFET portion during formation of the RSD in the NFET portion. Extensions are ion implanted into the ETSOI underneath the gate structure in the NFET portion.

Abstract translation: 一种形成半导体结构的方法，其包括具有PFET部分和NFET部分的极薄的绝缘体上硅（ETSOI）半导体结构，PFET部分中的栅极结构和NFET部分，高质量氮化物间隔物 PFET部分中的栅极结构和NFET部分以及PFET部分中的掺杂多面外延硅锗升高源极/漏极（RSD）。 在PFET部分的RSD上形成非晶硅层。 在与NFET部分中的高质量氮化物相邻的ETSOI上形成刻面外延硅RSD。 PFET部分中的非晶层防止在NFET部分中形成RSD期间在PFET部分中的外延生长。 扩展件被离子注入到NFET部分中的栅极结构下面的ETSOI中。

公开(公告)号：US20140015014A1

公开(公告)日：2014-01-16

申请号：US13545224

申请日：2012-07-10

Applicant: Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

Inventor： Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek ,  Thomas N. Adam

IPC: H01L21/20 ,  H01L21/336 ,  H01L29/78

CPC classification number: H01L27/088 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/0257 ,  H01L21/02576 ,  H01L21/02579 ,  H01L21/28008 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823437 ,  H01L21/84 ,  H01L29/167 ,  H01L29/6653 ,  H01L29/66545 ,  H01L29/66606 ,  H01L29/7834 ,  H01L29/7848

Abstract: A method including providing a semiconductor substrate including a first semiconductor device and a second semiconductor device, the first and second semiconductor devices including dummy spacers, dummy gates, and extension regions; protecting the second semiconductor device with a mask; removing the dummy spacers from the first semiconductor device; and depositing in-situ doped epitaxial regions on top of the extension regions of the first semiconductor device.

Abstract translation: 一种包括提供包括第一半导体器件和第二半导体器件的半导体衬底的方法，所述第一和第二半导体器件包括虚设衬垫，虚拟栅极和延伸区域; 用掩模保护第二半导体器件; 从第一半导体器件去除虚设间隔物; 以及在所述第一半导体器件的所述延伸区域的顶部上沉积原位掺杂的外延区域。

公开(公告)号：US20140001554A1

公开(公告)日：2014-01-02

申请号：US13534407

申请日：2012-06-27

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Ali Khakifirooz ,  Alexander Reznicek

IPC: H01L21/8238 ,  G06F17/50 ,  H01L27/12

CPC classification number: H01L29/0847 ,  H01L21/823412 ,  H01L21/823418 ,  H01L21/823481 ,  H01L21/84 ,  H01L23/485 ,  H01L27/1203 ,  H01L29/0653

Abstract: A method of forming a semiconductor structure includes providing an active layer and forming adjacent gate structures on the active layer. The gate structures each have sidewalls such that first spacers are formed on the sidewalls. A raised region is epitaxially grown on the active layer between the adjacent gate structures and at least one trench that extends through the raised region and through the active region is formed, whereby the at least one trench separates the raised region into a first raised region corresponding to a first transistor and a second raised region corresponding to a second transistor. The first raised region and second raised region are electrically isolated by the at least one trench.

Abstract translation: 形成半导体结构的方法包括提供有源层并在有源层上形成相邻的栅极结构。 栅极结构各自具有侧壁，使得第一间隔件形成在侧壁上。 凸起区域在相邻栅极结构之间的有源层上外延生长，并且形成延伸穿过凸起区域并通过有源区域的至少一个沟槽，由此至少一个沟槽将凸起区域分隔成对应于第一凸起区域 涉及对应于第二晶体管的第一晶体管和第二升高区域。 第一凸起区域和第二凸起区域由至少一个沟槽电隔离。

公开(公告)号：US20130292766A1

公开(公告)日：2013-11-07

申请号：US13463402

申请日：2012-05-03

Applicant: Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  Kangguo Cheng ,  Bruce B. Doris ,  Balasubramanian S. Haran ,  Pranita Kulkarni ,  Alexander Reznicek

IPC: H01L27/12

CPC classification number: H01L27/1203 ,  H01L21/84

Abstract: A semiconductor integrated circuit is provided and includes a first field effect transistor (FET) device and a second FET device formed on a semiconductor substrate. The first FET device has raised source/drain (RSD) structures grown at a first height. The second FET device has RSD structures grown at a second height greater than the first height such that a threshold voltage of the second FET device is greater than a threshold voltage of the first FET device.

Abstract translation: 提供了半导体集成电路，并且包括形成在半导体衬底上的第一场效应晶体管（FET）器件和第二FET器件。 第一FET器件提高了在第一高度生长的源极/漏极（RSD）结构。 第二FET器件具有在大于第一高度的第二高度处生长的RSD结构，使得第二FET器件的阈值电压大于第一FET器件的阈值电压。

公开(公告)号：US20130193492A1

公开(公告)日：2013-08-01

申请号：US13360823

申请日：2012-01-30

Applicant: THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

Inventor： THOMAS N. ADAM ,  Kangguo Cheng ,  Hong He ,  Ali Khakifirooz ,  Jinghong Li ,  Alexander Reznicek

IPC: H01L29/78 ,  H01L21/20

CPC classification number: H01L21/0245 ,  H01L21/02381 ,  H01L21/02447 ,  H01L21/02507 ,  H01L21/02529 ,  H01L21/0262 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/66636 ,  H01L29/7848

Abstract: An improved silicon carbon film structure is disclosed. The film structure comprises multiple layers of silicon carbon and silicon. The multiple layers form stress film structures that have increased substitutional carbon content, and serve to induce stresses that improve carrier mobility for certain types of field effect transistors.

Abstract translation: 公开了一种改进的硅碳膜结构。 膜结构包括多层硅碳和硅。 多层形成具有增加的取代碳含量的应力膜结构，并且用于诱导改善某些类型的场效应晶体管的载流子迁移率的应力。

公开(公告)号：US20130126944A1

公开(公告)日：2013-05-23

申请号：US13303248

申请日：2011-11-23

Applicant: Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

Inventor： Thomas N. Adam ,  David L. Harame ,  Qizhi Liu ,  Alexander Reznicek

IPC: H01L29/70 ,  H01L21/331

CPC classification number: H01L21/0262 ,  H01L21/02381 ,  H01L21/02439 ,  H01L21/02447 ,  H01L21/0245 ,  H01L21/02521 ,  H01L21/02529 ,  H01L21/02532 ,  H01L21/02576 ,  H01L21/02579 ,  H01L29/0817 ,  H01L29/1004 ,  H01L29/41708 ,  H01L29/66242 ,  H01L29/7371

Abstract: A heterojunction bipolar transistor (HBT) may include an n-type doped crystalline collector formed in an upper portion of a crystalline silicon substrate layer; a p-type doped crystalline p+Si1-xGex layer, formed above the n-type doped collector, that forms a p-type doped internal base of the HBT; a crystalline silicon cap formed on the p-type doped crystalline p+Si1-xGex layer, in which the crystalline silicon cap includes an n-type impurity and forms an n-type doped emitter of the HBT; and an n-type doped crystalline silicon emitter stack formed within an opening through an insulating layer to an upper surface of the crystalline silicon cap.

Abstract translation: 异质结双极晶体管（HBT）可以包括在晶体硅衬底层的上部形成的n型掺杂晶体集电极; 形成在n型掺杂集电极上方的p型掺杂晶体p + Si1-xGex层，其形成HBT的p型掺杂内部基极; 形成在p型掺杂结晶p + Si1-xGex层上的晶体硅帽，其中晶体硅帽包括n型杂质并形成HBT的n型掺杂发射极; 以及形成在通过绝缘层的开口内的晶体硅帽的上表面的n型掺杂晶体硅发射极堆叠。