Priority arbitration of coexisting wireless topologies
    1.
    发明授权
    Priority arbitration of coexisting wireless topologies 有权
    共存无线拓扑优先仲裁

    公开(公告)号:US08769176B1

    公开(公告)日:2014-07-01

    申请号:US13585544

    申请日:2012-08-14

    摘要: A system including a first communication module to transmit or receive data via an antenna in accordance with a first communication standard; a second communication module to transmit or receive data via the antenna in accordance with a second communication standard; and an arbitration module. The arbitration module outputs a first mutual grant where both the first communication module and the second communication module are able to simultaneously transmit data via the antenna; a second mutual grant where both the first communication module and the second communication module are able to simultaneously receive data via the antenna; a third mutual grant where the first communication module and the second communication module are able to simultaneously transmit and receive data, respectively, via the antenna; and a fourth mutual grant where the first communication module and the second communication module are able to simultaneously receive and transmit data, respectively, via the antenna.

    摘要翻译: 一种系统,包括:第一通信模块,用于根据第一通信标准通过天线发送或接收数据; 第二通信模块,用于根据第二通信标准经天线发送或接收数据; 和仲裁模块。 仲裁模块输出第一相互授权,其中第一通信模块和第二通信模块都能够经由天线同时发送数据; 第二相互授权,其中第一通信模块和第二通信模块都能够经由天线同时接收数据; 第三互补授权,其中第一通信模块和第二通信模块能够分别经由天线同时发送和接收数据; 以及第四相互授权,其中第一通信模块和第二通信模块能够分别经由天线同时接收和发送数据。

    System and method for dithering with reduced memory
    3.
    发明授权
    System and method for dithering with reduced memory 有权
    减少记忆抖动的系统和方法

    公开(公告)号:US07236269B2

    公开(公告)日:2007-06-26

    申请号:US10288781

    申请日:2002-11-05

    IPC分类号: H04N1/405

    CPC分类号: G09G3/2059

    摘要: A dithering system yielding two-dimensional dither functioning is implemented without line memories. For each primary input color, a feedback loop outputs an color input signal plus error that can be preset to different values. The desired result is that vertical artifacts on a display formed from the output signals are relocated to different locations on consecutive display lines. If signal magnitude from the feedback loop output exceeds the magnitude of the video system creating the display, signal magnitude is preset to a value representing error at the start of the display line.

    摘要翻译: 实现了产生二维抖动功能的抖动系统而没有行存储器。 对于每个主要输入颜色,反馈回路输出颜色输入信号加上可以预设为不同值的错误。 期望的结果是,由输出信号形成的显示器上的垂直伪像被重定位到连续显示行上的不同位置。 如果来自反馈环路输出的信号幅度超过创建显示器的视频系统的幅度,信号幅度被预设为表示在显示行开始处的误差的值。

    Active pixel sensor using CMOS technology with reverse biased photodiodes
    4.
    发明授权
    Active pixel sensor using CMOS technology with reverse biased photodiodes 失效
    有源像素传感器采用CMOS技术,具有反向偏置光电二极管

    公开(公告)号:US5900623A

    公开(公告)日:1999-05-04

    申请号:US909162

    申请日:1997-08-11

    摘要: An active pixel sensor implemented with CMOS technology that employs a plurality of photocells, each including a photodiode to sense illumination and a separate storage node with a stored charge that is discharged during an integration period by the photocurrent generated by the photodiode. Each photocell includes a switching network that couples the photocurrent to the storage node only during the integration period while ensuring that a relatively constant voltage is maintained across the photodiode during integration and non-integration periods. The transistors in the switching network operate in a forward active subthreshold region, ensuring linear operation and the diode voltage is clamped to a small positive voltage so that the diode is always reverse-biased. A source-follower generates a output signal correlated to the charge on the storage node that is coupled to column output circuitry that samples the signal. An operational scheme is employed wherein the storage node is first set to a defined voltage, the photocurrent is allowed to discharge the storage node and then the remaining charge coupled as a first signal to the column output circuitry, which samples and stores the first signal. The storage node is then reset to the same defined voltage and the resulting charge on the storage node is coupled as a second signal to the column output circuitry. The column output circuitry computes the difference of the first and second signals, which provides a reliable measure of the photocurrent during the integration period.

    摘要翻译: 使用CMOS技术实现的有源像素传感器,其采用多个光电池,每个光电池包括用于感测照明的光电二极管和具有在积分周期期间由光电二极管产生的光电流而放电的存储电荷的单独存储节点。 每个光电池包括仅在积分周期期间将光电流耦合到存储节点的切换网络,同时确保在积分和非积分周期期间跨越光电二极管保持相对恒定的电压。 开关网络中的晶体管工作在正向有源亚阈值区域,确保线性操作,并将二极管电压钳位到小的正电压,使得二极管总是反向偏置。 源跟随器产生与存储节点上的电荷相关联的输出信号,其耦合到对该信号进行采样的列输出电路。 采用操作方案,其中首先将存储节点设置为定义的电压,允许光电流将存储节点放电,然后将剩余电荷作为第一信号耦合到列输出电路,其中采样并存储第一信号。 存储节点然后被复位到相同的限定电压,并且存储节点上产生的电荷作为第二信号耦合到列输出电路。 列输出电路计算第一和第二信号的差异,这提供了在积分期间光电流的可靠测量。

    Skew code generator for measuring pulses width using a delay line
    5.
    发明授权
    Skew code generator for measuring pulses width using a delay line 失效
    歪斜码发生器,用于使用延迟线测量脉冲宽度

    公开(公告)号:US5138320A

    公开(公告)日:1992-08-11

    申请号:US614189

    申请日:1990-11-14

    IPC分类号: G01R25/00 H03K5/00 H03K5/13

    摘要: A skew code generator for digitally quantizing the width of a pulse. A series connected string of identical voltage controllable delay elements is supplied with the pulse, which is sensed as it passes through each of the delay elements. Output signals are developed in response to the leading edge of the pulse and are latched in response to the trailing edge of the pulse. An encoder generates a binary output from the latched output signals, which is indicative of the width of the pulse.

    摘要翻译: 用于数字量化脉冲宽度的偏斜码发生器。 提供具有相同电压可控延迟元件的串联串联的脉冲,当脉冲通过每个延迟元件时被感测。 响应于脉冲的前沿而产生输出信号,并且响应于脉冲的后沿被锁存。 编码器从锁存的输出信号产生二进制输出,其表示脉冲的宽度。

    WiMAX enhanced sleep mode
    6.
    发明授权
    WiMAX enhanced sleep mode 有权
    WiMAX增强睡眠模式

    公开(公告)号:US08660617B1

    公开(公告)日:2014-02-25

    申请号:US11642817

    申请日:2006-12-19

    IPC分类号: H04M1/00

    摘要: Power consumption is managed in a subscriber station of a communication system. The subscriber station is engaged in a sleep mode, including reducing a frequency of a system clock of the subscriber station. When the subscriber station receives, while in the sleep mode, a message having downlink transmission parameters while, the frequency of the system clock of the subscriber station is increased to process the message. After processing the message, the frequency of the system clock is reduced.

    摘要翻译: 在通信系统的用户台中管理功耗。 用户台进入休眠模式,包括降低订户站的系统时钟的频率。 当用户站在休眠模式下接收到具有下行链路传输参数的消息时,增加用户站的系统时钟的频率以处理消息。 处理消息后,系统时钟的频率就会降低。

    Multi-level piconet data aggregation
    7.
    发明授权
    Multi-level piconet data aggregation 有权
    多级微微网数据聚合

    公开(公告)号:US08457088B1

    公开(公告)日:2013-06-04

    申请号:US12763446

    申请日:2010-04-20

    IPC分类号: H04W4/00 H04B7/212 H04J3/24

    摘要: An example embodiment includes an apparatus. The apparatus includes piconet logic for establishing a multi-level piconet hierarchy having a top level piconet and a lower level piconet(s). The top level piconet includes the apparatus and a master controller(s). The apparatus is a master device in the top level piconet. Master controllers are slave devices in the top level piconet. A lower level piconet includes a master controller and a sub-controller(s). Master controllers are masters in the lower level piconet. Sub-controllers are slave devices in the lower level piconet. The apparatus includes time division multiplexing logic to solicit and control aggregated communication with master controllers. The aggregated communication comprises data from the master controller and data from a sub-controller(s). The apparatus includes de-aggregation logic to receive the aggregated communication and to separate data.

    摘要翻译: 示例实施例包括一种装置。 该装置包括用于建立具有顶级微微网和较低级微微网的多级微微网层级的微微网逻辑。 顶级微微网包括设备和主控制器。 该设备是顶级微微网中的主设备。 主控制器是顶级微微网中的从设备。 较低级微微网包括主控制器和子控制器。 主控制器是下级微微网的主人。 子控制器是下级微微网中的从设备。 该装置包括时分复用逻辑,用于请求和控制与主控制器的聚合通信。 聚合通信包括来自主控制器的数据和来自子控制器的数据。 该装置包括用于接收聚合通信和分离数据的解聚合逻辑。

    System-on-chip power reduction through dynamic clock frequency
    8.
    发明授权
    System-on-chip power reduction through dynamic clock frequency 有权
    通过动态时钟频率进行片上功耗降低

    公开(公告)号:US08281170B1

    公开(公告)日:2012-10-02

    申请号:US12645840

    申请日:2009-12-23

    IPC分类号: G06F1/32

    摘要: A dynamic clock frequency module includes a request evaluation module configured to generate a sum of requests to utilize a system bus from a plurality of modules. A frequency assignment module is configured to calculate a clock frequency for the system bus in response to the requests and adjust the clock frequency between at least two non-zero frequency values. A pulse stretch module is configured to increase a period of time that at least one of the requests is asserted in response to the sum.

    摘要翻译: 动态时钟频率模块包括:请求评估模块,被配置为生成从多个模块中使用系统总线的请求总和。 频率分配模块被配置为响应于该请求计算系统总线的时钟频率,并且调整至少两个非零频率值之间的时钟频率。 脉冲拉伸模块被配置为增加响应于总和而要求至少一个请求的时间段。

    WLAN TDM protocol
    10.
    发明授权
    WLAN TDM protocol 有权
    WLAN TDM协议

    公开(公告)号:US07751374B2

    公开(公告)日:2010-07-06

    申请号:US11311890

    申请日:2005-12-19

    IPC分类号: H04J3/00

    摘要: A wireless network device comprises an RF transceiver that transmits and receives data packets and that periodically transmits or receives a beacon. A control module communicates with the RF transceiver, determines a default interframe space (IFS) time based on the beacon, and selects one of the default IFS time and a second IFS time that is less than or equal to the default IFS time based on a number of data packets received after the beacon.

    摘要翻译: 无线网络设备包括发射和接收数据分组并且周期性地发送或接收信标的RF收发器。 控制模块与RF收发器进行通信,基于信标确定默认的帧间间隔(IFS)时间,并且基于该信标选择默认IFS时间和小于或等于默认IFS时间的第二IFS时间之一 信标后接收的数据包数。