公开(公告)号：US07482247B1

公开(公告)日：2009-01-27

申请号：US11524502

申请日：2006-09-19

申请人： George D. Papasouliotis ,  Raihan M. Tarafdar ,  Ron Rulkins ,  Dennis M. Hausmann ,  Jeff Tobin ,  Adrianne K. Tipton ,  Bunsen Nie ,  Wai-Fan Yau ,  Brian G. Lu ,  Timothy M. Archer ,  Sasson Roger Somekh

发明人： George D. Papasouliotis ,  Raihan M. Tarafdar ,  Ron Rulkins ,  Dennis M. Hausmann ,  Jeff Tobin ,  Adrianne K. Tipton ,  Bunsen Nie ,  Wai-Fan Yau ,  Brian G. Lu ,  Timothy M. Archer ,  Sasson Roger Somekh

IPC分类号： H01L21/311

CPC分类号： H01L21/3141 ,  C23C16/045 ,  C23C16/44 ,  H01L21/02164 ,  H01L21/02214 ,  H01L21/0228 ,  H01L21/3105 ,  H01L21/31116 ,  H01L21/31608 ,  H01L21/76224 ,  H01L21/76837

摘要： Conformal nanolaminate dielectric deposition and etch back processes that can fill high aspect ratio (typically at least 5:1, for example 6:1), narrow width (typically sub 0.13 micron, for example 0.1 micron or less) gaps with significantly reduced incidence of voids or weak spots involve the use of any suitable confirmal dielectric deposition technique and a dry etch back. The etch back part of the process involves a single step or an integrated multi-step (for example, two-step) procedure including an anisotropic dry etch followed by an isotropic dry etch. The all dry deposition and etch back process in a single tool increases throughput and reduces handling of wafers resulting in more efficient and higher quality nanolaminate dielectric gap fill operations.

摘要翻译： 可以满足高纵横比（通常至少5:1，例如6:1），窄宽度（通常为0.13微米，例如0.1微米或更小）的间隙的保形纳米酸盐电介质沉积和回蚀工艺，显着降低 空隙或弱点涉及使用任何合适的确认电介质沉积技术和干法回蚀。 该方法的回蚀部分涉及包括各向异性干法蚀刻以及各向同性干蚀刻的单步骤或集成多步骤（例如两步）程序。 在单个工具中的全部干沉积和回蚀工艺增加了生产量并减少了晶片的处理，从而产生了更有效和更高质量的纳米层间介质间隙填充操作。

公开(公告)号：US08795482B1

公开(公告)日：2014-08-05

申请号：US13572483

申请日：2012-08-10

申请人： Steven T. Mayer ,  Marshall R. Stowell ,  John S. Drewery ,  Richard S. Hill ,  Timothy M. Archer ,  Avishai Kepten

发明人： Steven T. Mayer ,  Marshall R. Stowell ,  John S. Drewery ,  Richard S. Hill ,  Timothy M. Archer ,  Avishai Kepten

IPC分类号： C25D5/02 ,  C25F3/16

CPC分类号： B23H5/08 ,  C25F3/16 ,  H01L21/02068 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/7684

摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.

摘要翻译： 提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

公开(公告)号：US08268154B1

公开(公告)日：2012-09-18

申请号：US12860787

申请日：2010-08-20

申请人： Steven T. Mayer ,  John S. Drewery ,  Richard S. Hill ,  Timothy M. Archer ,  Avishai Kepten

发明人： Steven T. Mayer ,  John S. Drewery ,  Richard S. Hill ,  Timothy M. Archer ,  Avishai Kepten

IPC分类号： C25D5/02

CPC分类号： B23H5/08 ,  C25F3/16 ,  H01L21/02068 ,  H01L21/2885 ,  H01L21/32115 ,  H01L21/7684

摘要： Methods and apparatus are provided for planar metal plating on a workpiece having a surface with recessed regions and exposed surface regions; comprising the steps of: causing a plating accelerator to become attached to said surface including the recessed and exposed surface regions; selectively removing the plating accelerator from the exposed surface regions without performing substantial metal plating on the surface; and after removal of plating accelerator is at least partially complete, plating metal onto the surface, whereby the plating accelerator remaining attached to the surface increases the rate of metal plating in the recessed regions relative to the rate of metal plating in the exposed surface regions.

摘要翻译： 提供了用于在具有凹陷区域和暴露表面区域的表面的工件上进行平面金属电镀的方法和装置; 包括以下步骤：使电镀加速器附着到包括凹入和暴露的表面区域的所述表面; 选择性地从暴露的表面区域去除电镀加速器，而不在表面上进行实质的金属电镀; 在去除电镀促进剂至少部分完成后，将金属镀在表面上，由此保持附着在表面上的电镀加速剂相对于露出的表面区域中的金属电镀速率增加凹陷区域中的金属电镀速率。

公开(公告)号：US06909190B2

公开(公告)日：2005-06-21

申请号：US09788105

申请日：2001-02-16

申请人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

发明人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

IPC分类号： H01L21/302 ,  H01L21/3065 ,  H01L21/314 ,  H01L21/316 ,  H01L21/768 ,  H01L23/48

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76822

摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

摘要翻译： 提供了用于在衬底上制造用于双镶嵌应用的电介质结构的电介质结构和方法。 该方法包括在衬底上形成阻挡层，在阻挡层上形成无机介电层，并在无机介电层上形成低介电常数层。 在该优选示例中，该方法还包括使用第一蚀刻化学物质在低介电常数层中形成沟槽，以及使用第二蚀刻化学在无机介电层中形成通孔，使得通孔在沟槽内。 在另一具体实例中，无机介电层可以是未掺杂的TEOS氧化物或氟掺杂的氧化物，并且低介电常数层可以是碳掺杂氧化物（C氧化物）或其它低K电介质。

公开(公告)号：US06251770B1

公开(公告)日：2001-06-26

申请号：US09346156

申请日：1999-06-30

申请人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

发明人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

IPC分类号： H01L214763

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76822

摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

摘要翻译： 提供了用于在衬底上制造用于双镶嵌应用的电介质结构的电介质结构和方法。 该方法包括在衬底上形成阻挡层，在阻挡层上形成无机介电层，并在无机介电层上形成低介电常数层。 在该优选示例中，该方法还包括使用第一蚀刻化学物质在低介电常数层中形成沟槽，以及使用第二蚀刻化学在无机介电层中形成通孔，使得通孔在沟槽内。 在另一具体实例中，无机介电层可以是未掺杂的TEOS氧化物或氟掺杂的氧化物，并且低介电常数层可以是碳掺杂氧化物（C氧化物）或其它低K电介质。

公开(公告)号：US07060605B2

公开(公告)日：2006-06-13

申请号：US09785999

申请日：2001-02-16

申请人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

发明人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76822

摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry, and forming a via in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In another specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

摘要翻译： 提供了用于在衬底上制造用于双镶嵌应用的电介质结构的电介质结构和方法。 该方法包括在衬底上形成阻挡层，在阻挡层上形成无机介电层，并在无机介电层上形成低介电常数层。 在该优选示例中，该方法还包括使用第一蚀刻化学物质在低介电常数层中形成沟槽，以及使用第二蚀刻化学在无机介电层中形成通孔，使得通孔在沟槽内。 在另一具体实例中，无机介电层可以是未掺杂的TEOS氧化物或氟掺杂的氧化物，并且低介电常数层可以是碳掺杂氧化物（C氧化物）或其它低K电介质。

公开(公告)号：US07501339B2

公开(公告)日：2009-03-10

申请号：US11389428

申请日：2006-03-23

申请人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

发明人： Jay E. Uglow ,  Nicolas J. Bright ,  Dave J. Hemker ,  Kenneth P. MacWilliams ,  Jeffrey C. Benzing ,  Timothy M. Archer

IPC分类号： H01L21/4763

CPC分类号： H01L21/76835 ,  H01L21/02126 ,  H01L21/02164 ,  H01L21/022 ,  H01L21/02304 ,  H01L21/31116 ,  H01L21/314 ,  H01L21/31633 ,  H01L21/76807 ,  H01L21/76822

摘要： A dielectric structure and method for making a dielectric structure for dual-damascene applications over a substrate are provided. The method includes forming a barrier layer over the substrate, forming an inorganic dielectric layer over the barrier layer, and forming a low dielectric constant layer over the inorganic dielectric layer. In this preferred example, the method also includes forming a trench in the low dielectric constant layer using a first etch chemistry. The etching is timed to etch through a partial thickness of the low dielectric constant layer and the first etch chemistry is optimized to a selected low dielectric constant material. The method further includes forming a via hole in the inorganic dielectric layer using a second etch chemistry, such that the via is within the trench. In a specific example, the inorganic dielectric layer can be an un-doped TEOS oxide or a fluorine doped oxide, and the low dielectric constant layer can be a carbon doped oxide (C-oxide) or other low K dielectrics.

摘要翻译： 提供了用于在衬底上制造用于双镶嵌应用的电介质结构的电介质结构和方法。 该方法包括在衬底上形成阻挡层，在阻挡层上形成无机介电层，并在无机介电层上形成低介电常数层。 在该优选示例中，该方法还包括使用第一蚀刻化学法在低介电常数层中形成沟槽。 刻蚀蚀刻通过低介电常数层的部分厚度，并且第一蚀刻化学物质被优化成所选择的低介电常数材料。 该方法还包括使用第二蚀刻化学品在无机介电层中形成通孔，使得通孔在沟槽内。 在具体实例中，无机介电层可以是未掺杂的TEOS氧化物或氟掺杂的氧化物，并且低介电常数层可以是碳掺杂氧化物（C氧化物）或其它低K电介质。