公开(公告)号：US07825777B1

公开(公告)日：2010-11-02

申请号：US11393489

申请日：2006-03-30

Applicant: Tingjun Wen ,  David Walter Carr ,  Tadeusz Kwasniewski

Inventor： Tingjun Wen ,  David Walter Carr ,  Tadeusz Kwasniewski

IPC: G05B1/00 ,  H03K19/20 ,  H03K19/094 ,  G06F7/00

CPC classification number: G06F7/026

Abstract: An integrated circuit comparator is provided that determines non-strict inequalities between operands applied thereto. Each comparator includes at least one n-bit comparator cell. This comparator cell is configured to determine a non-strict inequality between a first n-bit operand (e.g., A[n−1, . . . , 0]) and a second n-bit operand (e.g., B[n−1, . . . , 0]). The comparator cell determines the non-strict inequality by computing a control output signal Co (or its complement), where: C o = ( … ⁡ ( ( C i ⁡ ( A 0 + B 0 _ ) + A 0 ⁢ B 0 _ ) ⁢ ( A 1 + B 1 _ ) + A 1 ⁢ B 1 _ ) ⁢ … ⁡ ( A n - 2 + B n - 2 _ ) + A n - 2 ⁢ B n - 2 _ ) ⁢ ( A n - 1 + B n - 1 _ ) + A n - 1 ⁢ B n - 1 _ , “n” is a positive integer greater than one and Ci is a control input signal that specifies an interpretation to be given to the control output signal Co.

Abstract translation: 提供集成电路比较器，其确定施加到其上的操作数之间的非严格不等式。 每个比较器包括至少一个n位比较器单元。 该比较器单元被配置为确定第一n位操作数（例如，A [n-1，...，0]）和第二n位操作数之间的非严格不等式（例如，B [n-1 ，...，0]）。 比较器单元通过计算控制输出信号Co（或其补码）来确定非严格不等式，其中：C o =（...⁡（（C 0⁡（A 0 + B 0 _）+ A 0 B 0 _ ）（A 1 + B 1 _）+ A 1 B 1 _）...⁡（A n-2 + B n-2 _）+ A n-2 B n-2 _）（A n- 1 + B n - 1 _）+ A n - 1 B n - 1 _，“n”是大于1的正整数，Ci是指定给予控制输出信号Co的解释的控制输入信号 。

公开(公告)号：US07822916B1

公开(公告)日：2010-10-26

申请号：US11554958

申请日：2006-10-31

Applicant: Tingjun Wen

Inventor： Tingjun Wen

IPC: G06F12/00

CPC classification number: G11C15/00

Abstract: A search engine device includes a lookup circuit, such as a content addressable memory (CAM) array. This lookup circuit is configured to generate multiple active match signals in response to detecting multiple matches between a search operand applied to said lookup circuit and multiple entries therein, during a search operation. A priority sequencer circuit is also provided. This priority sequencer circuit, which is electrically coupled to outputs of the lookup circuit, is configured to sequentially encode each of the multiple active match signals according to priority.

Abstract translation: 搜索引擎设备包括诸如内容可寻址存储器（CAM）阵列之类的查找电路。 该查找电路被配置为响应于在搜索操作期间检测应用于所述查找电路的搜索操作数和其中的多个条目之间的多个匹配来生成多个有效匹配信号。 还提供优先顺序器电路。 电耦合到查找电路的输出的该优先顺控器电路被配置为根据优先顺序对多个有效匹配信号中的每一个进行顺序编码。

公开(公告)号：US07355890B1

公开(公告)日：2008-04-08

申请号：US11553202

申请日：2006-10-26

Applicant: Tingjun Wen

Inventor： Tingjun Wen

IPC: G11C16/04

CPC classification number: G11C15/04

Abstract: Content addressable memory (CAM) devices have CAM cells therein that are electrically coupled to a NAND-type compare circuit. This NAND-type compare circuit is responsive to a first operand (K) containing true and complementary bits of an applied search key and a second operand (D) containing true and complementary bits of a stored search word. The NAND-type compare circuit includes a first string of transistors connected end-to-end in series from a first terminal to a second terminal and a second string of transistors connected end-to-end in series from the first terminal to the second terminal. This first string of transistors has gate terminals responsive to the first operand and the second string of transistors has gate terminals responsive to the second operand.

Abstract translation: 内容可寻址存储器（CAM）器件具有电耦合到NAND型比较电路的CAM单元。 该NAND型比较电路响应于包含所应用的搜索关键字的真和互补位的第一操作数（K）和包含存储的搜索词的真和互补位的第二操作数（D）。 NAND型比较电路包括从第一端子到第二端子串联连接的第一串晶体管和从第一端子串联连接到第二端子的第二串联晶体管， 。 该第一串晶体管具有响应于第一操作数的栅极端子，并且第二串晶体管具有响应第二操作数的栅极端子。

公开(公告)号：US07298636B1

公开(公告)日：2007-11-20

申请号：US11393284

申请日：2006-03-30

Applicant: Tingjun Wen ,  Tadeusz Kwasniewski

Inventor： Tingjun Wen ,  Tadeusz Kwasniewski

IPC: G11C15/00

CPC classification number: G11C15/04

Abstract: A multi-functional match cell is responsive to first and second n-bit operands and configured so that the match cell operates as an n-bit range match cell when the first and second n-bit operands are equivalent, as an n-bit NOR-type CAM cell when the second n-bit operand is masked and as an n-bit NAND-type CAM cell when the first n-bit operand is masked, where “n” is a positive integer greater than one.

Abstract translation: 多功能匹配单元响应于第一和第二n位操作数，并且被配置为使得当第一和第二n位操作数相等时，匹配单元作为n位范围匹配单元操作，作为n位NOR 当第二n位操作数被屏蔽时作为n位的CAM单元，并且当第一n位操作数被屏蔽时作为n位的NAND型的CAM单元，其中“n”是大于1的正整数。