公开(公告)号：US07518167B2

公开(公告)日：2009-04-14

申请号：US11033729

申请日：2005-01-13

申请人： Tokuhiko Tamaki

发明人： Tokuhiko Tamaki

IPC分类号： H01L29/41

CPC分类号： H01L21/823871 ,  H01L27/11 ,  Y10S438/927

摘要： A semiconductor device includes: a p-type MIS transistor having a first gate electrode including silicon doped with p-type impurities; an n-type MIS transistor having a second gate electrode including silicon doped with n-type impurities; and a shared line which connects the p-type MIS transistor and the n-type MIS transistor and serves as a path of a power supply current or a ground current, the shared line including silicided silicon. The first gate electrode and the second gate electrode have silicided top portions, respectively, to establish electrical connection therebetween and the shared line has a line width larger than the line widths of the first gate electrode and the second gate electrode.

摘要翻译： 半导体器件包括：p型MIS晶体管，其具有包含掺杂有p型杂质的硅的第一栅电极; n型MIS晶体管，具有包含掺杂n型杂质的硅的第二栅电极; 以及连接p型MIS晶体管和n型MIS晶体管并用作电源电流或接地电流的路径的共享线路，共享线路包括硅化硅。 第一栅极电极和第二栅极电极分别具有硅化顶部以在其间建立电连接，并且共享线具有大于第一栅电极和第二栅电极的线宽的线宽。

公开(公告)号：US5753066A

公开(公告)日：1998-05-19

申请号：US712880

申请日：1996-09-12

申请人： Masafumi Kubota ,  Noboru Nomura ,  Tokuhiko Tamaki

发明人： Masafumi Kubota ,  Noboru Nomura ,  Tokuhiko Tamaki

IPC分类号： H01J37/32 ,  H05H1/00

CPC分类号： H01J37/32091 ,  H01J37/32155 ,  H01J37/32165

摘要： An apparatus for generating plasma is disclosed. The apparatus comprises: a plasma chamber; pairs of parallel plate electrodes; and a power supply for applying high-frequency powers on the pairs of electrodes. The frequencies of the high-frequency powers and the phase difference between the high-frequency powers are adjusted so as to cause each of electrons in the plasma to move in a circular path. A dense and highly uniform plasma is generated at a low pressure level, by utilizing the phenomenon of the oscillation, revolution or cycloidal motion of electrons in a high-frequency electric field formed between the parallel plate electrodes. This plasma is suitable for etching in the LSI fabrication process.

摘要翻译： 公开了一种用于产生等离子体的装置。 该装置包括：等离子体室; 成对平行板电极; 以及用于在所述电极对上施加高频功率的电源。 调整高频功率的频率和高频功率之间的相位差，使得等离子体中的每个电子以圆形路径移动。 通过利用形成在平行板电极之间的高频电场中的电子的振荡，旋转或摆线运动的现象，在低压水平下产生致密且高度均匀的等离子体。 该等离子体适用于LSI制造工艺中的蚀刻。

公开(公告)号：US5436424A

公开(公告)日：1995-07-25

申请号：US80824

申请日：1993-06-24

申请人： Ichiro Nakayama ,  Noboru Nomura ,  Tokuhiko Tamaki ,  Mitsuhiro Okuni ,  Masafumi Kubota

发明人： Ichiro Nakayama ,  Noboru Nomura ,  Tokuhiko Tamaki ,  Mitsuhiro Okuni ,  Masafumi Kubota

IPC分类号： H01L21/302 ,  H01J37/32 ,  H01L21/3065 ,  H05H1/46 ,  B23K10/00

CPC分类号： H01J37/32091 ,  H01J37/32165

摘要： A plasma generating apparatus includes a vacuum chamber having an insulated inner surface, more than two electrodes arranged on the insulated inner surface of the vacuum chamber, a high frequency applying device for applying high frequencies having different phases in order of positions of the electrodes, and a holder on which an object to be processed is placed. In the apparatus, a magnetic field is produced under plural alternating electric fields, so that electrons in a plasma generating portion are rotated to generate high density plasma under a high vacuum when the high frequencies are applied to the electrodes to generate the plasma and a specified process such as etching, CVD, or doping is carried on the object by reaction products generated at the portion.

摘要翻译： 一种等离子体发生装置，包括具有绝缘内表面的真空室，布置在真空室绝缘内表面上的多于两个电极的高频施加装置，用于按照电极位置的顺序施加具有不同相位的高频; 放置待处理物体的支架。 在该装置中，在多个交变电场下产生磁场，使得当将高频施加到电极以产生等离子体和指定的等离子体时，等离子体产生部分中的电子在高真空下旋转以产生高密度等离子体 通过在该部分产生的反应产物在物体上进行诸如蚀刻，CVD或掺杂的工艺。

公开(公告)号：US5424905A

公开(公告)日：1995-06-13

申请号：US40297

申请日：1993-03-30

申请人： Noboru Nomura ,  Kenji Harafuji ,  Masafumi Kubota ,  Tokuhiko Tamaki ,  Mitsuhiro Ohkuni ,  Ichiro Nakayama

发明人： Noboru Nomura ,  Kenji Harafuji ,  Masafumi Kubota ,  Tokuhiko Tamaki ,  Mitsuhiro Ohkuni ,  Ichiro Nakayama

IPC分类号： H01J37/32 ,  H01J37/317

CPC分类号： H01J37/32302 ,  H01J37/32192 ,  H01J2237/3341

摘要： Three electrodes are disposed at lateral sides of a plasma generating chamber of an etching apparatus serving as a plasma generating apparatus. A sample stage is disposed at a lower part of the plasma generating chamber, and an opposite electrode is disposed at an upper part thereof. High frequency electric power having a first frequency is supplied to the sample stage and the opposite electrode. Respectively supplied to the three electrodes 4, 5, 6 are high frequency electric powers which are oscillated by a three-phase magnetron, which have a second frequency different from the first frequency and of which respective phases are successively different by about 120.degree. from one another, thus forming a rotational electric field in the plasma generating chamber.

摘要翻译： 在作为等离子体发生装置的蚀刻装置的等离子体发生室的侧面设置三个电极。 样品台设置在等离子体发生室的下部，相对电极设置在其上部。 具有第一频率的高频电力被提供给样品台和相对电极。 分别提供给三个电极4,5,6的是​​由三相磁控管振荡的高频电力，三相磁控管具有与第一频率不同的第二频率，并且各相相互相差约120度 从而在等离子体发生室中形成旋转电场。

公开(公告)号：US5296095A

公开(公告)日：1994-03-22

申请号：US785300

申请日：1991-10-30

申请人： Yutaka Nabeshima ,  Tokuhiko Tamaki

发明人： Yutaka Nabeshima ,  Tokuhiko Tamaki

IPC分类号： H01L21/311 ,  H01L21/00

CPC分类号： H01L21/31116

摘要： A dry etching method for dry etching a silicon oxide film or a multilayer oxide film thereof which enables formation of contact window to good dimensional precision and with stable etching configuration in the process of film etching at submicron level. A compound gas containing a C element or S element or Cl element, and F element (e.g., CF.sub.4) is used as a principal gas, and a compound gas containing a C element and two or more of H elements (e.g., CH.sub.2 F.sub.2) as an additive gas is used, in the process of dry etching silicon oxide film or a multilayer film thereof. By using principal and additive gases having good step coverage of deposit produced by plasma reaction, it is possible to eliminate any etching residue and form contact windows having stable etching configuration and good dimensional accuracy in the process of film etching at submicron level. By using a compound gas containing a greater number of H element atoms than C element atoms, the deposit on the etching side wall can be a soluble one having a low F element content, such as (C.sub.x H.sub.y)n polymer, and can be readily removed through after-etching washing.

摘要翻译： 用于干蚀刻氧化硅膜或其多层氧化物膜的干蚀刻方法，其能够在亚微米级别的膜蚀刻过程中形成接触窗以具有良好的尺寸精度和稳定的蚀刻构造。 使用含有C元素或S元素或Cl元素和F元素（例如CF 4）的复合气体作为主要气体，并且将包含C元素和两种或多种H元素（例如CH 2 F 2）的化合物气体用作 在氧化硅干法蚀刻或其多层膜的过程中，使用添加气体。 通过使用通过等离子体反应产生的沉积具有良好阶梯覆盖的主要和附加气体，可以在亚微米级的膜蚀刻过程中消除任何蚀刻残留物并形成具有稳定蚀刻构造和良好尺寸精度的接触窗口。 通过使用含有比C元素原子多的H元素原子的复合气体，蚀刻侧壁上的沉积物可以是具有低F元素含量的可溶性沉积物，例如（C x H y）n聚合物，并且可以容易地除去 通过蚀刻后的洗涤。

公开(公告)号：US4845048A

公开(公告)日：1989-07-04

申请号：US268604

申请日：1988-11-07

申请人： Tokuhiko Tamaki ,  Masafumi Kubota

发明人： Tokuhiko Tamaki ,  Masafumi Kubota

IPC分类号： H01L21/76 ,  H01L21/32 ,  H01L21/762

CPC分类号： H01L21/32 ,  H01L21/76264 ,  H01L21/76281 ,  Y10S148/043 ,  Y10S148/051 ,  Y10S148/117

摘要： A method of fabricating a semiconductor device which includes:(1) a step of forming an opening in a silicon substrate using a first silicon oxide film and a first silicon nitride film formed on the silicon substrate as masks,(2) a step of forming a second silicon oxide film and a second silicon nitride film on the side wall of the opening by the reduced pressure CVD method and anisotropic etching method,(3) a step of performing isotropic dry etching using the first and second silicon oxide films as masks, and(4) a step of performing heat treatment in an oxidizing atmosphere using the first and second silicon nitride films as masks.Thereby, uniform isotropic etching may be accomplished by use of the dry etching method.

摘要翻译： 一种制造半导体器件的方法，包括：（1）使用第一氧化硅膜和在硅衬底上形成的第一氮化硅膜作为掩模在硅衬底中形成开口的步骤，（2）形成步骤 通过减压CVD法和各向异性蚀刻法在开口侧壁上的第二氧化硅膜和第二氮化硅膜，（3）使用第一和第二氧化硅膜作为掩模进行各向同性干蚀刻的步骤， 和（4）使用第一和第二氮化硅膜作为掩模在氧化气氛中进行热处理的步骤。 因此，均匀的各向同性蚀刻可以通过使用干蚀刻方法来实现。

公开(公告)号：US08344426B2

公开(公告)日：2013-01-01

申请号：US12976153

申请日：2010-12-22

申请人： Naoki Kotani ,  Tokuhiko Tamaki

发明人： Naoki Kotani ,  Tokuhiko Tamaki

IPC分类号： H01L27/10 ,  H01L21/335

CPC分类号： H01L27/0207 ,  H01L27/092

摘要： A semiconductor device includes a plurality of first cells having a first cell height, and a plurality of second cells having a second cell height. Each of the first cells has a first MIS transistor of a first conductivity type, and a substrate contact region of a second conductivity type. Each of the second cells has a second MIS transistor of the first conductivity type, a power supply region of the first conductivity type, and a first extended region of the first conductivity type that is silicidated at a surface thereof. The first cell height is greater than the second cell height.

摘要翻译： 半导体器件包括具有第一单元高度的多个第一单元和具有第二单元高度的多个第二单元。 每个第一单元具有第一导电类型的第一MIS晶体管和第二导电类型的基板接触区域。 每个第二单元具有第一导电类型的第二MIS晶体管，第一导电类型的电源区域和在其表面处被硅化的第一导电类型的第一延伸区域。 第一个单元格高度大于第二个单元格高度。

公开(公告)号：US20110006374A1

公开(公告)日：2011-01-13

申请号：US12886036

申请日：2010-09-20

申请人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

发明人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

IPC分类号： H01L27/092

CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

摘要翻译： 包括SRAM部分和逻辑电路部分的半导体器件包括：第一n型MIS晶体管，包括第一n型栅极，其形成有插入在SRAM中的半导体衬底的第一元件形成区域上的第一栅极绝缘膜 部分; 以及第二n型MIS晶体管，其包括形成有第二栅极绝缘膜的第二n型栅电极，所述第二栅极绝缘膜插入在所述逻辑电路部分中的所述半导体衬底的第二元件形成区域上。 第一n型栅电极中的第一n型杂质的第一杂质浓度低于第二n型栅极中的第二n型杂质的第二杂质浓度。

公开(公告)号：US07824987B2

公开(公告)日：2010-11-02

申请号：US12539203

申请日：2009-08-11

申请人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

发明人： Tokuhiko Tamaki ,  Naoki Kotani ,  Shinji Takeoka

IPC分类号： H01L21/8234 ,  H01L21/336

CPC分类号： H01L21/823842 ,  H01L21/82345 ,  H01L21/823456 ,  H01L21/82385 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11 ,  H01L27/1116 ,  Y10S257/903

摘要： A semiconductor device including a SRAM section and a logic circuit section includes: a first n-type MIS transistor including a first n-type gate electrode formed with a first gate insulating film interposed on a first element formation region of a semiconductor substrate in the SRAM section; and a second n-type MIS transistor including a second n-type gate electrode formed with a second gate insulating film interposed on a second element formation region of the semiconductor substrate in the logic circuit section. A first impurity concentration of a first n-type impurity in the first n-type gate electrode is lower than a second impurity concentration of a second n-type impurity in the second n-type gate electrode.

摘要翻译： 包括SRAM部分和逻辑电路部分的半导体器件包括：第一n型MIS晶体管，包括第一n型栅极，其形成有插入在SRAM中的半导体衬底的第一元件形成区域上的第一栅极绝缘膜 部分; 以及第二n型MIS晶体管，其包括形成有第二栅极绝缘膜的第二n型栅电极，所述第二栅极绝缘膜插入在所述逻辑电路部分中的所述半导体衬底的第二元件形成区域上。 第一n型栅电极中的第一n型杂质的第一杂质浓度低于第二n型栅极中的第二n型杂质的第二杂质浓度。

公开(公告)号：US07560200B2

公开(公告)日：2009-07-14

申请号：US11376191

申请日：2006-03-16

申请人： Tokuhiko Tamaki

发明人： Tokuhiko Tamaki

IPC分类号： G03F1/00 ,  G06F17/50

CPC分类号： G03F1/36

摘要： In the mask data generation method, optical simulation is performed on a dual gate including a first gate portion doped with an impurity of a first conductivity type and a second gate portion doped with an impurity of a second conductivity type for correcting design data including the dual gate. Specifically, a first dimesion difference of the first gate portion between a resist dimension obtained in lithography and a dimension obtained after dryetch following the lithography is calculated. Next, a second dimension difference of the second gate portion between a resist dimension obtained in the lithography and a dimension obtained after the dryetch is calculated. Furthermore, after calculating a difference between the first dimension difference and the second dimension difference, the first gate portion or the second gate portion is corrected in the design data by using the calculated difference. Thereafter, the optical simulation is executed on the design data having been corrected by using the difference, so as to generate mask data.

摘要翻译： 在掩模数据生成方法中，在包括掺杂有第一导电类型的杂质的第一栅极部分和掺杂有第二导电类型的杂质的第二栅极部分的双栅极上进行光学模拟，用于校正包括双重 门。 具体地说，计算出在光刻中得到的抗蚀剂尺寸与光刻后的干蚀后获得的尺寸之间的第一栅极部分的第一尺寸差。 接下来，计算第二栅极部分在光刻中获得的抗蚀剂尺寸与在干蚀刻之后获得的尺寸之间的第二尺寸差。 此外，在计算第一尺寸差和第二尺寸差之间的差值之后，通过使用计算出的差异，在设计数据中校正第一门部分或第二门部分。 此后，对通过使用差异校正的设计数据执行光学模拟，以便生成掩模数据。