公开(公告)号：US06801996B2

公开(公告)日：2004-10-05

申请号：US09778069

申请日：2001-02-07

申请人： Moriyasu Banno ,  Tomoaki Shoda ,  Hiroshi Itaya ,  Tomotaka Saito

发明人： Moriyasu Banno ,  Tomoaki Shoda ,  Hiroshi Itaya ,  Tomotaka Saito

IPC分类号： G06F932

CPC分类号： G06F9/30178

摘要： An instruction code conversion unit, an information processing system provided with the instruction code conversion unit and an instruction code generation method for generating instruction codes which are converted by the instruction code conversion unit are described. The efficiency of coding of the program is improved by making use of an existing processor as selected is used without modification. An instruction code conversion unit performs conversion of the address of a native instruction code to the address of the corresponding compressed instruction code in a program memory by shifting the address of the native instruction code as outputted from the processor to the right by one bit.

摘要翻译： 指令代码转换单元，设置有指令代码转换单元的信息处理系统和用于产生由指令代码转换单元转换的指令代码的指令代码生成方法。 通过使用未经修改地选择的现有处理器来改进程序的编码效率。 指令代码转换单元通过将从处理器输出的本地指令代码的地址向右移位一位，来执行本地指令代码的地址到程序存储器中对应的压缩指令代码的地址的转换。

公开(公告)号：US4641278A

公开(公告)日：1987-02-03

申请号：US666449

申请日：1984-10-30

申请人： Tomotaka Saito

发明人： Tomotaka Saito

IPC分类号： G06F12/00 ,  G06F9/315 ,  G06F12/06 ,  G11C13/00

CPC分类号： G06F9/30032

摘要： A memory device with a register interchange function includes a register file with a plurality of registers, one of which is selected according to select signals, and a register select circuit. The internal memory state of the register select circuit is updated according to the internal memory state and a pair of interchange data for interchanging the select signals. In a register selection mode, a level setting of the select data is performed depending on the internal memory state and the register select data.

摘要翻译： 具有寄存器交换功能的存储器件包括具有多个寄存器的寄存器文件，其中一个寄存器根据选择信号被选择，寄存器选择电路。 根据内部存储器状态更新寄存器选择电路的内部存储器状态，以及一对用于交换选择信号的互换数据。 在寄存器选择模式中，根据内部存储器状态和寄存器选择数据执行选择数据的电平设置。

公开(公告)号：US4583092A

公开(公告)日：1986-04-15

申请号：US558477

申请日：1983-12-06

申请人： Tomotaka Saito

发明人： Tomotaka Saito

IPC分类号： G06F15/02 ,  G06F3/02 ,  H03K17/687 ,  H03M11/20 ,  H04Q9/00 ,  G06F3/00

CPC分类号： H03K17/6871 ,  H03M11/20

摘要： A sweep circuit of a key matrix, has an output circuit wherein a series circuit of a pair of transistors with a terminal interposed therebetween is inserted between a power supply and a reference potential, and a timing pulse for selectively turning on one of said pair of transistors is supplied to the gates of the pair of transistors so as to produce a key scanning signal; an input circuit wherein a transistor is inserted between a terminal connecting an output side of the key matrix and the reference potential, the key matrix being connected between the terminals of the output and input circuits; and a transistor which switches to insert a current limiting resistor between the reference potential and the transistor at the reference potential side in each of the input and output circuits in the non-read-in mode.

摘要翻译： 按键矩阵的扫描电路具有输出电路，其中一对晶体管的串联电路插入在电源和参考电位之间，并且定时脉冲用于选择性地导通所述一对 晶体管被提供给该对晶体管的栅极，以产生键扫描信号; 一个输入电路，其中一个晶体管被插在连接在键矩阵的一个输出端的一个终端和该参考电位之间，该键矩阵连接在输出和输入电路的端子之间; 以及晶体管，其切换以在非读入模式下在每个输入和输出电路中的参考电位和参考电位侧的晶体管之间插入限流电阻。

公开(公告)号：US5041744A

公开(公告)日：1991-08-20

申请号：US374069

申请日：1989-06-30

申请人： Hideo Sakai ,  Tomotaka Saito

发明人： Hideo Sakai ,  Tomotaka Saito

IPC分类号： H03K5/08 ,  H03F3/345 ,  H03K5/24 ,  H03K19/096

CPC分类号： H03F3/345 ,  H03K5/249

摘要： The present invention provides a logic circuit comprising a first power terminal, a second power terminal set at a higher potential than the first power terminal, a first FET of a first conductivity having a current path coupled to the first power terminal, a second FET of a second conductivity having a current path coupled to the second power terminal, and an input terminal commonly coupled to gate terminals of the first and second FETs, the first FET and the second FET having a relationship expressed approximately by the following equation: ##EQU1## where R.sub.S is a resistance of a resistor element parasitically produced between the first power terminal and the current path of the first FET. R.sub.D is a resistance of a resistor element parasitically produced between the second power terminal and the current path of the second FET, W.sub.N is a channel width of the first FET, W.sub.P is a channel width of the second FET, L.sub.N is a channel length of the first FET, L.sub.P is a channel length of the second FET, .mu..sub.N is a first carrier mobililty of the first FET, and .mu..sub.P is a second carrier mobility of the second FET.

公开(公告)号：US5036223A

公开(公告)日：1991-07-30

申请号：US525041

申请日：1990-05-18

申请人： Hideo Sakai ,  Kiyoharu Oikawa ,  Tomotaka Saito

发明人： Hideo Sakai ,  Kiyoharu Oikawa ,  Tomotaka Saito

IPC分类号： H03K5/24

CPC分类号： H03K5/249

摘要： An inverter circuit according to this invention includes n- and p-type field effect transistors having predetermined wiring resistances and gates and drains connected with each other, a first power source connected to the source of the n-type field effect transistor, a power source connected to the source of the p-type field effect transistor, and first and second negative feedback switching transistors connected in parallel between the gates and the drains of the n- and p-type field effect transistors. Assuming that the channel length and width of the first insulating gate field effect transistor are L.sub.N and W.sub.N, respectively, and the wiring resistance thereof is R.sub.S, that the channel length and width of the second insulating gate field effect transistor are L.sub.P and W.sub.P, respectively, and the wiring resistance thereof is R.sub.D, and that carrier mobilities of the first and second insulating gate field effect transistors are .mu..sub.N and .mu..sub.P, respectively, a relation represented by: ##EQU1## is approximately satisfied. A voltage corresponding to a difference between a reference voltage and a comparison input is input from the connected gates, and data is output from the connected drains.

摘要翻译： 根据本发明的逆变器电路包括具有预定布线电阻的n型和p型场效应晶体管和彼此连接的栅极和漏极，连接到n型场效应晶体管的源极的第一电源， 连接到p型场效应晶体管的源极，以及并联连接在n型和p型场效应晶体管的栅极和漏极之间的第一和第二负反馈开关晶体管。 假设第一绝缘栅场效应晶体管的沟道长度和宽度分别为LN和WN，其布线电阻为RS，则第二绝缘栅场效应晶体管的沟道长度和宽度分别为LP和WP ，其布线电阻为RD，第一绝缘栅场效应晶体管和第二绝缘栅场效应晶体管的载流子迁移率分别为μN和μP，大致满足由下式表示的关系：。 从连接的门输入对应于参考电压和比较输入之间的差的电压，并且从连接的排水口输出数据。

公开(公告)号：US4973975A

公开(公告)日：1990-11-27

申请号：US390770

申请日：1989-08-08

申请人： Akihiro Yamazaki ,  Tomotaka Saito ,  Hideo Sakai

发明人： Akihiro Yamazaki ,  Tomotaka Saito ,  Hideo Sakai

IPC分类号： H03M1/38 ,  H03M1/12 ,  H03M1/34

CPC分类号： H03M1/1295 ,  H03M1/1225

摘要： One of analog input voltages applied to a plurality of analog input terminals is selected by means of analog switches connected to the respective analog input terminals and supplied to a common terminal. In this case, each of the analog switches permits selective supply of the potential of a corresponding one of the plurality of analog input terminals in response to a control signal supplied from a controller. The common terminal is connected to the positive input terminal of a comparator. The comparator compares the voltage with a digital output value from the controller which is converted into an analog voltage by means of a D/A converter. Further, the controller generates a preset control signal in an inhibition period during which supply of a voltage from the plurality of analog input terminals to the common terminal is inhibited. An initial potential setting circuit sets the potential of the common terminal to a voltage level equal to substantially one-half the maximum voltage level of the analog input voltages applied to the plurality of analog input terminals.

公开(公告)号：US4814639A

公开(公告)日：1989-03-21

申请号：US238998

申请日：1988-08-29

申请人： Tomotaka Saito ,  Hiroaki Murakami ,  Yuhji Fukushima ,  Masami Konishi

发明人： Tomotaka Saito ,  Hiroaki Murakami ,  Yuhji Fukushima ,  Masami Konishi

IPC分类号： H01L21/822 ,  G01R31/28 ,  G01R31/3185 ,  H01L21/66 ,  H01L21/82 ,  H01L27/04 ,  H03K3/26 ,  H03K17/56

CPC分类号： G01R31/318513 ,  G01R31/2884 ,  G01R31/318505 ,  Y10S257/923

摘要： At least first and second IC-chip equivalent regions having functions available from conventional one-chip IC device are formed on a single semiconductor substrate. An output of the second region is supplied to an input terminal of the first region. The output of the second region is also delivered at an external terminal in response to a test signal through a multiplexer or a bidirectional buffer.

摘要翻译： 至少具有可从常规单片IC器件获得的功能的第一和第二IC芯片等效区域形成在单个半导体衬底上。 第二区域的输出被提供给第一区域的输入端子。 响应于通过复用器或双向缓冲器的测试信号，第二区域的输出也在外部端子处传送。

公开(公告)号：US4760279A

公开(公告)日：1988-07-26

申请号：US66094

申请日：1987-06-24

申请人： Tomotaka Saito ,  Kazumasa Ando ,  Akira Wada

发明人： Tomotaka Saito ,  Kazumasa Ando ,  Akira Wada

IPC分类号： H03K5/1252 ,  H03K5/22

CPC分类号： H03K5/1252

摘要： A noise cancelling circuit includes a delay circuit for delaying an input signal which is supplied to an input terminal, and a signal processing circuit responsive to the input signal and an output signal from the delay circuit, to generate an output signal corresponding to the input signal. The signal processing circuit has a first switching circuit, which includes first and second switching elements connected in series between a first power supply terminal and an output, and a second switching circuit, which includes third and fourth switching elements connected in series between a second power supply terminal and the output, wherein the first and third switching elements are responsive to the aforementioned input signal, by which they are set in mutually opposite conduction states, and the second and fourth switching elements are responsive to the output signal of the delay circuit, by which they too are set in mutually opposite conduction states.

摘要翻译： 噪声消除电路包括用于延迟提供给输入端的输入信号的延迟电路和响应于输入信号的信号处理电路和来自延迟电路的输出信号，以产生对应于输入信号的输出信号 。 信号处理电路具有包括串联连接在第一电源端子和输出端之间的第一和第二开关元件的第一开关电路和包括第三和第四开关元件的第二开关元件，第三开关元件和第四开关元件串联连接在第二电源 供电端子和输出端，其中第一和第三开关元件响应于上述输入信号，它们被设置为相互相反的导通状态，第二和第四开关元件响应延迟电路的输出信号， 由此它们也被设置在相互相反的导通状态。

公开(公告)号：US5307313A

公开(公告)日：1994-04-26

申请号：US659506

申请日：1991-02-22

申请人： Akihiro Yamazaki ,  Tomotaka Saito ,  Shuichi Ito

发明人： Akihiro Yamazaki ,  Tomotaka Saito ,  Shuichi Ito

IPC分类号： G11C29/14 ,  G01R31/317 ,  G06F1/24 ,  G06F11/22 ,  G06F13/26 ,  G06F15/78 ,  G11C17/00 ,  G11C29/00 ,  G11C8/02

CPC分类号： G06F13/26 ,  G01R31/31701

摘要： In a semiconductor integrated circuit for switching various functions in accordance with "H"/"L" level of a read output from EPROM cells or the like, a state of memory cells incorporated in the semiconductor is detected to switch a function state. The semiconductor integrated circuit is free from an inoperative state caused by indefinite values of an initial state (erasure state) as of the EPROM cells and the like, or is free from a state in which only a predetermined operation is performed. When a writing operation is performed to EPROM cells and the like in an initial state in advance, a function test for a semiconductor integrated circuit can be normally performed. A test time can be largely decreased compared with that of a conventional technique, and a production cost can be largely reduced.

摘要翻译： 在用于根据EPROM单元等的读取输出的“H”/“L”电平切换各种功能的半导体集成电路中，检测结合在半导体中的存储单元的状态以切换功能状态。 半导体集成电路没有由EPROM单元等的初始状态（擦除状态）的不确定值引起的不工作状态，或者不存在仅执行预定操作的状态。 当预先在初始状态下对EPROM单元等进行写入操作时，可以正常地进行半导体集成电路的功能测试。 与常规技术相比，测试时间可以大大降低，并且可以大大降低生产成本。

公开(公告)号：US5239194A

公开(公告)日：1993-08-24

申请号：US661816

申请日：1991-02-28

申请人： Satoshi Ohtani ,  Masayuki Yoshida ,  Nobutaka Kitagawa ,  Tomotaka Saito

发明人： Satoshi Ohtani ,  Masayuki Yoshida ,  Nobutaka Kitagawa ,  Tomotaka Saito

IPC分类号： H01L27/02

CPC分类号： H01L27/0266

摘要： A semiconductor substrate has a plurality of MOS transistors formed therein. Each of the transistors comprises high density diffusion regions having high impurity density and serving as source and drain, low density diffusion regions having low impurity density and extending in contact with the high density diffusion regions, respectively, a channel region formed between the low density diffusion regions, and a gate formed above the substrate and insulated from the channel region. One of the transistors has its drain connected to an input/output terminal. The low density diffusion region of the one has impurity density higher than that of the other. The channel length of the one is greater than that of the other.