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    Vital signal measurement device, and vital sign signal measurement system
    1.
    发明授权
    Vital signal measurement device, and vital sign signal measurement system 有权
    生命信号测量装置，生命信号测量系统

    公开(公告)号：US09572491B2

    公开(公告)日：2017-02-21

    申请号：US14421823

    申请日：2012-09-03

    申请人： Tatsuo Nakagawa ,  Tomoyuki Ishii ,  Akira Kotabe

    发明人： Tatsuo Nakagawa ,  Tomoyuki Ishii ,  Akira Kotabe

    IPC分类号： G08C19/22 ,  A61B5/00

    CPC分类号： A61B5/0022 ,  A61B5/0004 ,  A61B5/0006 ,  A61B5/0024 ,  A61B5/02125 ,  A61B5/0245 ,  A61B5/04325 ,  A61B5/7285

    摘要： A vital signal measurement system including a plurality of terminals aims to facilitate synchronization of each terminal with respect to other terminals. Each of the plurality of terminals (102) is provided with a first vital signal sensor (201) for measuring a vital signal, a first memory (205) for storing a first data which is based on the vital signal, and a first radio communication unit (206) for communicating with other terminals by radio. The first data is applied with a sequence number corresponding to the first data and the number indicates an order in which the first data is acquired. A first terminal (102b) included in the plurality of terminals performs resetting of the sequence number triggered by the synchronous signal which is received by the first radio communication unit.

    摘要翻译： 包括多个终端的重要信号测量系统旨在促进每个终端相对于其他终端的同步。 多个端子（102）中的每一个设置有用于测量生命信号的第一生命信号传感器（201），用于存储基于重要信号的第一数据的第一存储器（205）和第一无线电通信 单元（206），用于通过无线电与其他终端进行通信。 第一数据被应用与第一数据对应的序号，数字表示获取第一数据的顺序。 包括在多个终端中的第一终端（102b）执行由第一无线电通信单元接收的同步信号触发的序列号的重置。

    Semiconductor device
    2.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US08278700B2

    公开(公告)日：2012-10-02

    申请号：US13072211

    申请日：2011-03-25

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    INFORMATION PROCESSING TERMINAL AND POWER STATE MANAGEMENT APPARATUS
    3.
    发明申请
    INFORMATION PROCESSING TERMINAL AND POWER STATE MANAGEMENT APPARATUS 审中-公开
    信息处理终端和电力管理装置

    公开(公告)号：US20110261405A1

    公开(公告)日：2011-10-27

    申请号：US13088534

    申请日：2011-04-18

    申请人： Shuichi Ito ,  Tomoyuki Ishii ,  Masayuki Yusukaga ,  Tomohiro Iwase ,  Syunji Kamei

    发明人： Shuichi Ito ,  Tomoyuki Ishii ,  Masayuki Yusukaga ,  Tomohiro Iwase ,  Syunji Kamei

    IPC分类号： G06F3/12

    CPC分类号： G06F3/1204 ,  G06F1/3203 ,  G06F1/3284 ,  G06F3/1203 ,  G06F3/1212 ,  G06F3/1221 ,  G06F3/1229 ,  G06F3/1286 ,  G06F3/1292 ,  H04L12/12 ,  H04L67/125 ,  H04L67/18 ,  H04W4/023 ,  H04W4/33 ,  Y02D10/159 ,  Y02D10/1592

    摘要： The distance between an information processing terminal and each image forming apparatus is detected based on the position information of the information processing terminal and each image forming apparatus, and the difference in elevation and layout drawing are checked to determine whether or not the image forming apparatus is located in the same floor or room with the information processing terminal, whereby the image forming apparatus is selected, and a request to shift the power state to the power-on side is sent to the selected image forming apparatus. Further, the server device provides such power control as to acquire the information on the position and number of terminal devices in the started-up state and the information of the position of each image forming apparatus, and to select the image forming apparatus to be set to the power-on state out of plural image forming apparatuses, based on this information.

    摘要翻译： 基于信息处理终端和每个图像形成装置的位置信息来检测信息处理终端和每个图像形成装置之间的距离，并且检查图像形成装置是否为图像形成装置 位于与信息处理终端相同的楼层或房间中，由此选择图像形成装置，并且将向电源侧移动电力状态的请求发送到所选择的图像形成装置。 此外，服务器装置提供这样的功率控制以获得关于启动状态下的终端装置的位置和数量的信息以及每个图像形成装置的位置的信息，并且选择要设置的图像形成装置 到多个图像形成装置中的通电状态。

    Semiconductor memory device and manufacturing method of the same
    4.
    发明授权
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US07969760B2

    公开(公告)日：2011-06-28

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C5/06

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。

    Semiconductor device
    5.
    发明授权
    Semiconductor device 有权
    半导体器件

    公开(公告)号：US07939879B2

    公开(公告)日：2011-05-10

    申请号：US11896800

    申请日：2007-09-06

    申请人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    发明人： Taro Osabe ,  Tomoyuki Ishii ,  Kazuo Yano ,  Takashi Kobayashi

    IPC分类号： H01L29/792

    CPC分类号： H01L27/11521 ,  B82Y10/00 ,  G11C16/0433 ,  G11C16/0458 ,  G11C16/0483 ,  G11C16/0491 ,  G11C16/10 ,  G11C16/26 ,  G11C2216/06 ,  H01L27/115 ,  H01L29/42332 ,  H01L29/42348 ,  H01L29/7887

    摘要： For providing a cheap semiconductor memory device with improving reliability by level of a cell, in the place of escaping from defects on memory cells electrically, through such as ECC, and further for providing a cell structure enabling scaling-down in the vertical direction with maintaining the reliability, in a semiconductor memory device, upon which high-speeded read-out operation is required, a charge storage region is constructed with particles made from a large number of semiconductor charge storage small regions, each being independent, thereby increasing the reliability by the cell level.

    摘要翻译： 为了通过电池级提供具有提高可靠性的便宜的半导体存储器件，以代替通过诸如ECC的电存储器单元中的缺陷脱离，并且还用于提供能够在垂直方向上按比例缩小的单元结构，同时保持 在需要高速读出操作的半导体存储器件中的可靠性，电荷存储区域由大量半导体电荷存储小区域制成的粒子构成，各自独立，从而通过 细胞水平。

    Semiconductor memory device
    6.
    再颁专利
    Semiconductor memory device 有权
    半导体存储器件

    公开(公告)号：USRE41868E1

    公开(公告)日：2010-10-26

    申请号：US11708145

    申请日：2007-02-20

    申请人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    发明人： Toshiaki Sano ,  Tomoyuki Ishii ,  Kazuo Yano ,  Toshiyuki Mine

    IPC分类号： H01L29/76 ,  H01L29/788

    CPC分类号： B82Y10/00 ,  G11C11/5621 ,  G11C11/5628 ,  G11C11/5635 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C2216/08 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/66825 ,  H01L29/7883 ,  H01L29/7888 ,  H01L29/7889

    摘要： A memory cell with a small surface area is fabricated by forming source lines and data lines above and below and by running the channels to face up and down. The local data lines for each vertically stacked memory cell are connected to a global data line by way of separate selection by a molecular oxide semiconductor, and use of a large surface area is avoided by making joint use of peripheral circuits such as global data lines and sensing amplifiers by performing read and write operations in a timed multiplex manner. Moreover, data lines in multi-layers and memory cells (floating electrode cell) which are non-destructive with respect to readout are utilized to allow placement of memory cells at all intersecting points of word lines and data lines while having a folded data line structure. An improved noise tolerance is attained by establishing a standard threshold voltage for identical dummy cells even in any of the read verify, write verify and erase verify operations. A register to temporarily hold write data in a memory cell during writing is also used as a register to hold a flag showing that writing has ended during write verify. Also, a circuit comprised of one nMOS transistor is utilized as a means to change values on the write-end flag.

    摘要翻译： 通过在上下形成源极线和数据线，并且通过使通道正面上下而制造具有小表面积的存储单元。 每个垂直堆叠的存储单元的本地数据线通过分子氧化物半导体的单独选择连接到全局数据线，并且通过联合使用诸如全局数据线和外围电路的外围电路来避免使用大的表面积 通过以定时复用方式执行读和写操作来感测放大器。 此外，利用相对于读出非破坏性的多层和存储单元（浮动电极单元）中的数据线，以允许在字线和数据线的所有交叉点处放置存储单元，同时具有折叠的数据线结构 。 即使在读取验证，写入验证和擦除验证操作中的任何一个中，通过建立用于相同虚拟单元的标准阈值电压来获得改善的噪声容限。 在写入期间暂时保持写入数据在存储单元中的寄存器也被用作寄存器来保存写入验证期间写入结束的标志。 此外，由一个nMOS晶体管组成的电路被用作改变写入端标志的值的手段。

    METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE
    8.
    发明申请
    METHOD FOR FABRICATION OF SEMICONDUCTOR DEVICE 失效
    半导体器件制造方法

    公开(公告)号：US20080261357A1

    公开(公告)日：2008-10-23

    申请号：US11956858

    申请日：2007-12-14

    申请人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

    发明人： Norifumi KAMESHIRO ,  Toshiyuki Mine ,  Tomoyuki Ishii ,  Toshiaki Sano

    IPC分类号： H01L21/84

    CPC分类号： H01L29/66757 ,  H01L29/66613 ,  H01L29/66772

    摘要： After forming a source-drain material film on an insulator layer, an opening portion reaching the insulator layer is formed in the source-drain material film. Then, a channel having desired thickness and a gate insulator are sequentially formed on the insulator layer and the source-drain material film in the opening portion. Thereafter, a gate material film embedding the opening portion is formed on the gate insulator. Subsequently, a cap film is formed on the gate material film, thereby forming the gate made of the gate material film. Then, a mask layer is formed on the source-drain material film. Next, the source-drain material film not protected by the mask layer is removed while protecting the gate by the cap film, thereby leaving the source-drain material film on both sides of the gate. The source-drain material film on one side becomes the source and that on the other side becomes the drain.

    摘要翻译： 在绝缘体层上形成源极 - 漏极材料膜之后，在源极 - 漏极材料膜中形成到达绝缘体层的开口部分。 然后，在开口部分的绝缘体层和源极 - 漏极材料膜上依次形成具有期望厚度的沟道和栅极绝缘体。 此后，在栅极绝缘体上形成嵌入开口部的栅极材料膜。 随后，在栅极材料膜上形成盖膜，从而形成由栅极材料膜制成的栅极。 然后，在源极 - 漏极材料膜上形成掩模层。 接下来，除去未被掩模层保护的源极 - 漏极材料膜，同时通过盖膜保护栅极，从而在栅极的两侧留下源极 - 漏极材料膜。 一侧的源极 - 漏极材料膜成为源极，而另一侧的源极 - 漏极材料膜变成漏极。

    Semiconductor memory device and manufacturing method of the same
    10.
    发明申请
    Semiconductor memory device and manufacturing method of the same 有权
    半导体存储器件及其制造方法

    公开(公告)号：US20070285983A1

    公开(公告)日：2007-12-13

    申请号：US11790590

    申请日：2007-04-26

    申请人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    发明人： Tomoyuki Ishii ,  Yoshitaka Sasago ,  Hideaki Kurata ,  Toshiyuki Mine

    IPC分类号： G11C11/34 ,  H01L21/336

    CPC分类号： H01L27/0207 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11521 ,  H01L27/11524

    摘要： The invention provides a voltage applying structure having a reduced area penalty with respect to a data line. A wiring forming a global data line and a local data line formed in a p-type well region are connected via a select transistor. Two select lines are formed on a gate electrode of the select transistor. One select line is electrically connected to the gate electrode of the select transistor, however, the other select line is not connected to the select transistor. That is, an insulator film is formed between the select line and the gate electrode. As mentioned above, two select lines shorter than a gate length are provided on one select transistor. The select line is structured such as to be connected to the other select transistor.

    摘要翻译： 本发明提供一种相对于数据线具有减小的面积损失的电压施加结构。 形成在p型阱区中的全局数据线和局部数据线的布线经由选择晶体管连接。 在选择晶体管的栅电极上形成两条选择线。 一个选择线电连接到选择晶体管的栅电极，然而另一选择线不连接到选择晶体管。 也就是说，在选择线和栅电极之间形成绝缘膜。 如上所述，在一个选择晶体管上设置两条比栅极长度短的选择线。 选择线被构造成连接到另一个选择晶体管。