公开(公告)号：US09123581B2

公开(公告)日：2015-09-01

申请号：US13287569

申请日：2011-11-02

申请人： Toshihiko Saito ,  Yutaka Shionoiri ,  Kiyoshi Kato

发明人： Toshihiko Saito ,  Yutaka Shionoiri ,  Kiyoshi Kato

IPC分类号： G06K19/06 ,  H01L27/12 ,  G06K19/07 ,  H01L21/84

CPC分类号： H01L27/12 ,  G06K19/0701 ,  G06K19/0715 ,  G06K19/0723 ,  H01L21/84

摘要： An object of the present invention is to provide a semiconductor device which can obtain the high potential necessary for writing data to a memory, using a small circuit area. In the present invention, by using as input voltage of a booster circuit not the conventionally used output VDD of a regulator circuit 104, but rather an output VDD0 of a rectifier circuit portion 103, which is a higher potential than the VDD, the high potential necessary for writing data to a memory can be obtained with a small circuit area.

摘要翻译： 本发明的目的是提供一种使用小电路区域可以获得将数据写入存储器所需的高电位的半导体器件。 在本发明中，通过使用升压电路的输入电压而不是调节器电路104的常规使用的输出VDD，而是使用比VDD高的电压的整流电路部分103的输出VDD0， 可以以小的电路面积获得将数据写入存储器所必需的。

公开(公告)号：US08809853B2

公开(公告)日：2014-08-19

申请号：US13409316

申请日：2012-03-01

申请人： Toshihiko Saito ,  Kiyoshi Kato ,  Atsuo Isobe

发明人： Toshihiko Saito ,  Kiyoshi Kato ,  Atsuo Isobe

IPC分类号： H01L29/78 ,  H01L29/772

CPC分类号： H01L27/0688 ,  G11C16/0433 ,  H01L21/02565 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L29/408 ,  H01L29/4236 ,  H01L29/78 ,  H01L29/7869 ,  H01L29/78696

摘要： With a combination of a transistor including an oxide semiconductor material and a transistor including a semiconductor material other than an oxide semiconductor, a semiconductor device with a novel structure in which data can be retained for a long time and does not have a limitation on the number of writing can be obtained. When a connection electrode for connecting the transistor including a semiconductor material other than an oxide semiconductor to the transistor including an oxide semiconductor material is smaller than an electrode of the transistor including a semiconductor material other than an oxide semiconductor that is connected to the connection electrode, the semiconductor device with a novel structure can be highly integrated and the storage capacity per unit area can be increased.

摘要翻译： 通过包括氧化物半导体材料的晶体管和包括除了氧化物半导体之外的半导体材料的晶体管的组合，具有可以长时间保持数据并且对数字没有限制的新颖结构的半导体器件 的写作可以获得。 当用于将包括氧化物半导体的半导体材料的晶体管连接到包括氧化物半导体材料的晶体管的连接电极小于包含与连接电极连接的氧化物半导体以外的半导体材料的晶体管的电极时， 具有新颖结构的半导体器件可以高度集成，并且可以增加每单位面积的存储容量。

公开(公告)号：US08779488B2

公开(公告)日：2014-07-15

申请号：US13443027

申请日：2012-04-10

申请人： Toshihiko Saito

发明人： Toshihiko Saito

IPC分类号： H01L27/108

CPC分类号： H01L27/10805 ,  G11C11/405 ,  G11C16/0433 ,  H01L21/84 ,  H01L27/0288 ,  H01L27/1156 ,  H01L27/1203 ,  H01L27/1225 ,  H01L28/60 ,  H01L28/86 ,  H01L28/90

摘要： In the semiconductor memory device, one of a source and a drain of a first transistor is connected to one of a source and a drain of a second transistor, a gate of the first transistor is connected to one of a source and a drain of a third transistor and one of a pair of capacitor electrodes included in a capacitor, the other of the source and the drain of the first transistor and the other of the source and the drain of the third transistor are connected to a bit line, the other of the pair of capacitor electrodes included in the capacitor is connected to a common wiring, and the common wiring is grounded (GND). The common wiring has a net shape when seen from the above, and the third transistor is provided in a mesh formed by the common wiring.

摘要翻译： 在半导体存储器件中，第一晶体管的源极和漏极之一连接到第二晶体管的源极和漏极之一，第一晶体管的栅极连接到源极和漏极之一 第三晶体管和包括在电容器中的一对电容器电极中的一个，第一晶体管的源极和漏极中的另一个以及第三晶体管的源极和漏极中的另一个连接到位线，另一个 包括在电容器中的一对电容器电极连接到公共布线，并且公共布线接地（GND）。 当从上方观察时，公共布线具有净形状，并且第三晶体管设置在由公共布线形成的网格中。

公开(公告)号：US08507907B2

公开(公告)日：2013-08-13

申请号：US13015247

申请日：2011-01-27

申请人： Yasuyuki Takahashi ,  Toshihiko Saito

发明人： Yasuyuki Takahashi ,  Toshihiko Saito

IPC分类号： H01L27/112

CPC分类号： G11C16/26 ,  G11C16/0433 ,  G11C2216/26 ,  H01L27/112 ,  H01L27/11206 ,  H01L27/1225

摘要： It is to provide a semiconductor memory device in which high voltage is not needed in writing, a defect is less likely to occur, the writing time is short, and data cannot be rewritten without an increase in cost. The semiconductor memory device includes a memory element which includes a diode-connected first transistor, a second transistor whose gate is connected to one terminal of a source electrode and a drain electrode of the diode-connected first transistor, and a capacitor connected to the one terminal of the source electrode and the drain electrode of the diode-connected first transistor and the gate of the second transistor.

摘要翻译： 提供一种在写入时不需要高电压的半导体存储器件，不太可能发生缺陷，写入时间短，并且在不增加成本的情况下不能重写数据。 该半导体存储器件包括存储元件，该存储元件包括二极管连接的第一晶体管，第二晶体管的栅极连接到源电极的一个端子和二极管连接的第一晶体管的漏极，以及连接到该二极管的第一晶体管的电容器 二极管连接的第一晶体管的源电极和漏电极以及第二晶体管的栅极。

公开(公告)号：US08421081B2

公开(公告)日：2013-04-16

申请号：US13331645

申请日：2011-12-20

申请人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

发明人： Kiyoshi Kato ,  Jun Koyama ,  Toshihiko Saito ,  Shunpei Yamazaki

IPC分类号： H01L21/02

CPC分类号： H01L27/1156 ,  G11C11/404 ,  H01L27/1225

摘要： The first transistor includes first and second electrodes which are a source and a drain, and a first gate electrode overlapping with a first channel formation region with an insulating film provided therebetween. The second transistor includes third and fourth electrodes which are a source and a drain, and a second channel formation region which is provided between a second gate electrode and a third gate electrode with insulating films provided between the second channel formation region and the second gate electrode and between the second channel formation region and the third gate electrode. The first and second channel formation regions contain an oxide semiconductor, and the second electrode is connected to the second gate electrode.

摘要翻译： 第一晶体管包括作为源极和漏极的第一和第二电极，以及与第一沟道形成区域重叠的第一栅电极，其间设置有绝缘膜。 第二晶体管包括作为源极和漏极的第三和第四电极以及设置在第二栅电极和第三栅极之间的第二沟道形成区，其中设置在第二沟道形成区和第二栅电极之间的绝缘膜 并且在第二通道形成区域和第三栅电极之间。 第一和第二沟道形成区域包含氧化物半导体，并且第二电极连接到第二栅电极。

公开(公告)号：US08406038B2

公开(公告)日：2013-03-26

申请号：US13094863

申请日：2011-04-27

申请人： Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

发明人： Toshihiko Saito ,  Takanori Matsuzaki ,  Shuhei Nagatsuka ,  Hiroki Inoue

IPC分类号： G11C11/24

CPC分类号： H01L29/78 ,  G11C11/403 ,  G11C11/406 ,  G11C16/0416 ,  G11C2211/4065 ,  H01L27/11521 ,  H01L27/1156 ,  H01L27/1207 ,  H01L27/1225

摘要： A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.

公开(公告)号：US08344435B2

公开(公告)日：2013-01-01

申请号：US12559086

申请日：2009-09-14

申请人： Toshihiko Saito

发明人： Toshihiko Saito

IPC分类号： H01L27/108

CPC分类号： H01L27/112 ,  H01L23/5252 ,  H01L27/11206 ,  H01L28/40 ,  H01L2924/0002 ,  H01L2924/00

摘要： To realize a semiconductor memory device whose capacitance value per unit area in a memory cell is increased without increase in the area of the memory cell. The memory cell includes a transistor, a memory element, a first capacitor, and a second capacitor. The first capacitor includes a semiconductor film, a gate insulating film, and a gate electrode which are included in the transistor and is formed at the same time as the transistor. The second capacitor includes an electrode which is included in the memory element and an insulating film and an electrode which are formed over the electrode. Further, the second capacitor is formed over the first capacitor. In this manner, the first capacitor and the second capacitor which are connected in parallel with the memory element are formed.

摘要翻译： 为了实现其存储单元中的每单位面积的电容值增加而不增加存储单元面积的半导体存储器件。 存储单元包括晶体管，存储元件，第一电容器和第二电容器。 第一电容器包括半导体膜，栅绝缘膜和栅电极，其包括在晶体管中并且与晶体管同时形成。 第二电容器包括包含在存储元件中的电极和形成在电极上的绝缘膜和电极。 此外，第二电容器形成在第一电容器上。 以这种方式，形成与存储元件并联连接的第一电容器和第二电容器。

公开(公告)号：US20120139872A1

公开(公告)日：2012-06-07

申请号：US13367634

申请日：2012-02-07

申请人： Kiyoshi KATO ,  Toshihiko SAITO

发明人： Kiyoshi KATO ,  Toshihiko SAITO

IPC分类号： G09G3/36 ,  G06F3/045

CPC分类号： G02F1/13338 ,  G02F1/13306 ,  G02F1/133305 ,  G02F1/133345 ,  G02F1/13439 ,  G02F1/13454 ,  G02F1/136213 ,  G02F1/1368 ,  G02F2201/123 ,  G06F3/0412 ,  G06F3/044 ,  G09G3/36 ,  H01L27/12 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/124 ,  H01L27/1255 ,  H01L27/1288 ,  H01L27/13 ,  H01L27/3244 ,  H01L29/78621 ,  H01L29/78645

摘要： A variable capacitor is formed from a pair of electrodes and a dielectric interposed between the electrodes over a substrate, and an external input is detected by changing capacitance of the variable capacitor by a physical or electrical force. Specifically, a variable capacitor and a sense amplifier are provided over the same substrate, and the sense amplifier reads the change of capacitance of the variable capacitor and transmits a signal in accordance with the input to a control circuit.

摘要翻译： 可变电容器由一对电极和位于基板之间的电极之间的电介质形成，并且通过用物理或电力改变可变电容器的电容来检测外部输入。 具体地说，在同一衬底上设置可变电容器和读出放大器，读出放大器读取可变电容器的电容变化，并根据输入将信号发送到控制电路。

公开(公告)号：US20120039126A1

公开(公告)日：2012-02-16

申请号：US13197845

申请日：2011-08-04

申请人： Toshihiko Saito

发明人： Toshihiko Saito

IPC分类号： G11C14/00 ,  G11C11/24

CPC分类号： G11C11/407 ,  G11C11/405 ,  G11C11/40615 ,  G11C16/0433 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3431

摘要： A method for driving a semiconductor memory device including a transistor with low leakage current between a source and a drain in an off state and capable of storing data for a long time is provided. In a matrix including a plurality of memory cells in each of which a drain of a write transistor, a gate of an element transistor, and one electrode of a capacitor are connected, a gate of the write transistor is connected to a write word line, and the other electrode of the capacitor is connected to a read word line. The amount of charge stored in the capacitor is checked by changing the potential of the read word line, and if the amount of charge has decreased beyond a predetermined amount, the memory cell is refreshed.

摘要翻译： 提供了一种用于驱动半导体存储器件的方法，该半导体存储器件包括在断开状态下的源极和漏极之间具有低漏电流的晶体管，并且能够长时间存储数据。 在包括写入晶体管的漏极，元件晶体管的栅极和电容器的一个电极的多个存储单元的矩阵中，写入晶体管的栅极连接到写入字线， 并且电容器的另一个电极连接到读取字线。 通过改变读取字线的电位来检查存储在电容器中的电荷量，并且如果电荷量已经减少超过预定量，则刷新存储器单元。

公开(公告)号：US20110228602A1

公开(公告)日：2011-09-22

申请号：US13044656

申请日：2011-03-10

申请人： Toshihiko Saito ,  Shuhei Nagatsuka

发明人： Toshihiko Saito ,  Shuhei Nagatsuka

IPC分类号： G11C14/00 ,  G11C16/04

CPC分类号： G11C16/26 ,  G11C11/404 ,  G11C11/405 ,  G11C14/00 ,  G11C16/0433

摘要： One of objects is to provide a nonvolatile memory device in which the occurrence of a defect in data writing is suppressed and whose area can be suppressed, or a semiconductor device including the nonvolatile memory device. A first memory portion including a nonvolatile memory element and a second memory portion (data buffer) for temporarily storing data in verifying operation in which whether the data is correctly written into the first memory portion is verified are provided. Further, the second memory portion includes a memory element and an insulated gate field effect transistor for controlling the holding of charge in the memory element; the off-state current or the leakage current of the transistor is extremely low.

摘要翻译： 其目的之一是提供一种非易失性存储器件，其中数据写入中的缺陷的发生被抑制并且其面积可被抑制，或者包括非易失性存储器件的半导体器件。 提供了一种包括非易失性存储元件和用于临时存储数据的第二存储器部分（数据缓冲器）的第一存储器部分，其被验证是否将数据正确写入第一存储器部分的验证操作。 此外，第二存储器部分包括用于控制存储元件中的电荷的保持的存储元件和绝缘栅场效应晶体管; 晶体管的截止电流或漏电流极低。