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13 条记录 (耗时 0.013 秒)

    Dry etching method
    1.
    发明授权
    Dry etching method 有权
    干蚀刻法

    公开(公告)号：US07192532B2

    公开(公告)日：2007-03-20

    申请号：US10475268

    申请日：2002-02-27

    申请人： Akiteru Koh ,  Toshihiro Miura ,  Takayuki Fukasawa ,  Akitaka Shimizu ,  Masato Kushibiki ,  Asao Yamashita ,  Fumihiko Higuchi

    发明人： Akiteru Koh ,  Toshihiro Miura ,  Takayuki Fukasawa ,  Akitaka Shimizu ,  Masato Kushibiki ,  Asao Yamashita ,  Fumihiko Higuchi

    IPC分类号： C03C25/68

    CPC分类号： H01J37/32082 ,  H01L21/28061 ,  H01L21/28123 ,  H01L21/32137

    摘要： A tungsten silicide layer (104) is etched by plasma etching using Cl2+O2 gas as etching gas. When etching of the tungsten silicide layer (104) is ended substantially, etching gas is switched to Cl2+O2+NF3 and over etching is performed by plasma etching. Etching process is ended under a state where a polysilicon layer (103) formed beneath the tungsten silicide layer (104) is slightly etched uniformly. Residual quantity of the polysilicon layer (103) can be made uniform as compared with prior art and a high quality semiconductor device can be fabricated stably.

    摘要翻译： 通过使用Cl 2 O 2 + O 2气体作为蚀刻气体的等离子体蚀刻来蚀刻硅化钨层（104）。 当钨硅化物层（104）的蚀刻基本上结束时，蚀刻气体被切换到Cl 2 + O 2 + N N 3 3并过度 通过等离子体蚀刻进行蚀刻。 在钨硅化物层（104）下方形成的多晶硅层（103）被均匀地微蚀刻的状态下结束蚀刻处理。 与现有技术相比，多晶硅层（103）的剩余量可以均匀，并且可以稳定地制造高质量的半导体器件。

    Semiconductor integrated circuit device and high frequency power amplifier module
    4.
    发明申请
    Semiconductor integrated circuit device and high frequency power amplifier module 有权
    半导体集成电路器件和高频功率放大器模块

    公开(公告)号：US20070049237A1

    公开(公告)日：2007-03-01

    申请号：US11511300

    申请日：2006-08-29

    申请人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

    发明人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

    IPC分类号： H04B1/44 ,  H04B1/28

    CPC分类号： H04B1/48

    摘要： Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.

    摘要翻译： SPDT开关中的开关特性得到改善，可以降低高功率插槽后的低功率插槽的上升延时。 SPDT开关的控制端子分别设有防回流电路。 防回流电路被配置为具有两个晶体管和二极管。 在传输模式中，例如，当高功率通过晶体管的时隙之后是低功率通过的时隙时，积聚在晶体管的栅极中的电荷被阻断。 在晶体管处于截止状态的情况下，立即放电晶体管的栅极中累积的电荷，使晶体管完全截止。

    Semiconductor integrated circuit device and high frequency power amplifier module
    8.
    发明授权
    Semiconductor integrated circuit device and high frequency power amplifier module 有权
    半导体集成电路器件和高频功率放大器模块

    公开(公告)号：US07650133B2

    公开(公告)日：2010-01-19

    申请号：US11511300

    申请日：2006-08-29

    申请人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

    发明人： Toshihiro Miura ,  Hitoshi Akamine ,  Yasushi Shigeno ,  Akishige Nakajima ,  Masahiro Tsuchiya

    IPC分类号： H04B1/16

    CPC分类号： H04B1/48

    摘要： Switching characteristics in an SPDT switch are improved to reduce the rise delay in a low power slot following after a high power slot. Control terminals of an SPDT switch are respectively provided with backflow prevention circuits. The backflow prevention circuit is configured to have two transistors and a diode. In a transmission mode, for example, when a time slot where a high power passes through transistors is followed by a time slot where a low power passes through, the electric charges accumulated in the gates of the transistors are blocked. In the case where the transistors are in the OFF state, the electric charges accumulated in the gates of the transistors are immediately discharged to allow the transistors to be completely turned OFF.

    摘要翻译： SPDT开关中的开关特性得到改善，可以降低高功率插槽后的低功率插槽的上升延时。 SPDT开关的控制端子分别设有防回流电路。 防回流电路被配置为具有两个晶体管和二极管。 在传输模式中，例如，当高功率通过晶体管的时隙之后是低功率通过的时隙时，积聚在晶体管的栅极中的电荷被阻断。 在晶体管处于截止状态的情况下，立即放电晶体管的栅极中累积的电荷，使晶体管完全截止。