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    Bus access arbiter and method of bus arbitration
    1.
    发明授权
    Bus access arbiter and method of bus arbitration 有权

    公开(公告)号：US09747231B2

    公开(公告)日：2017-08-29

    申请号：US14389410

    申请日：2012-12-27

    申请人： Toshiki Takeuchi

    发明人： Toshiki Takeuchi

    IPC分类号： G06F13/36 ,  G06F13/40 ,  G06F13/362 ,  G06F13/14

    CPC分类号： G06F13/362 ,  G06F13/4068

    摘要： A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.

    Printing apparatus
    3.
    发明授权
    Printing apparatus 有权
    印刷装置

    公开(公告)号：US08998402B2

    公开(公告)日：2015-04-07

    申请号：US13348430

    申请日：2012-01-11

    申请人： Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Kengo Nieda ,  Shigeru Toriihara

    发明人： Koichiro Kawaguchi ,  Toshiki Takeuchi ,  Kengo Nieda ,  Shigeru Toriihara

    IPC分类号： B41J2/165 ,  B41J11/00 ,  B41J3/54

    CPC分类号： B41J11/005 ,  B41J3/543 ,  B41J11/0025 ,  B41J11/0065

    摘要： A printing apparatus includes a print head for inkjet printing, and a guide disposed opposing the print head and configured to guide a back surface of a sheet being conveyed in a first direction. The back surface is a reverse surface of a surface being printed. The printing apparatus further includes a receiving unit disposed opposing the print head and configured to receive ink outside the sheet being conveyed, and a mechanism configured to change a position of the guide in a second direction relative to the receiving unit being fixed, according to a size of the sheet to be used. The second direction crosses the first direction.

    摘要翻译： 打印装置包括用于喷墨打印的打印头和与打印头相对布置的引导件，其被布置成引导沿第一方向传送的片材的后表面。 后表面是被印刷的表面的反面。 打印设备还包括一个接收单元，该接收单元设置成与打印头相对设置，并被配置为接收被输送的纸张外部的墨水;以及机构，其被配置为相对于被固定的接收单元在相对于接收单元固定的第二方向上改变引导件的位置， 要使用的纸张尺寸。 第二个方向穿过第一个方向。

    BUS ACCESS ARBITER AND METHOD OF BUS ARBITRATION
    4.
    发明申请
    BUS ACCESS ARBITER AND METHOD OF BUS ARBITRATION 有权
    总线访问ARBITER和总线仲裁方法

    公开(公告)号：US20150067213A1

    公开(公告)日：2015-03-05

    申请号：US14389410

    申请日：2012-12-27

    申请人： Toshiki Takeuchi

    发明人： Toshiki Takeuchi

    IPC分类号： G06F13/362 ,  G06F13/40

    CPC分类号： G06F13/362 ,  G06F13/4068

    摘要： A bus access arbiter includes an access mode judgment unit and a round robin arbitration unit. The access mode judgment unit judges, when bus access is generated from a plurality of masters M0 and M1, whether an access mode of each of the masters that are connected is a sequential access mode or a single access mode. The round robin arbitration unit dynamically switches an access arbitration method for arbitrating the bus access according to the access mode. The access mode judgment unit includes an access interval count unit, a sequential access number count unit, and an access mode state register that stores a state of the judged access mode for each of the masters, and updates the state of the access mode based on an access interval and the number of sequential access.

    摘要翻译： 总线访问仲裁器包括访问模式判断单元和循环仲裁单元。 访问模式判断单元当从多个主站M0和M1生成总线访问时，判断连接的每个主站的访问模式是顺序访问模式还是单次访问模式。 循环仲裁单元根据访问模式动态切换用于仲裁总线访问的访问仲裁方法。 访问模式判断单元包括访问间隔计数单元，顺序访问次数计数单元和存储模式状态寄存器，其存储每个主设备的所判断的访问模式的状态，并且基于 访问间隔和顺序访问次数。

    Synchronization processing circuit and synchronization processing method in wireless communication system
    5.
    发明授权
    Synchronization processing circuit and synchronization processing method in wireless communication system 有权
    无线通信系统中的同步处理电路和同步处理方法

    公开(公告)号：US08711902B2

    公开(公告)日：2014-04-29

    申请号：US13144481

    申请日：2009-12-21

    申请人： Toshiki Takeuchi

    发明人： Toshiki Takeuchi

    IPC分类号： H04B1/00

    CPC分类号： H04B1/7095 ,  H04B1/70735 ,  H04B1/7075 ,  H04B1/7093 ,  H04B2201/70711

    摘要： In a synchronization processing circuit in a wireless communication system, a correlation operation unit is designed to have a parallel structure which can be restructured to improve flexibility in order to cope with various synchronization processings in a plurality of radio systems.The synchronization processing circuit in the wireless communication system comprises a plurality of correlation operation modules 31 through 3N that execute correlation operation, each of which correlation operation modules includes a plurality of correlators 60, a plurality of shift registers 50 for shifting a correlation code, an interface which transfers a shifted correlation code to an adjacent correlation operation unit for timing correlation processing, and a correlation code selection unit 40 which selects an externally and individually applied correlation code for code correlation processing and a correlation code transferred from an adjacent correlation operation unit as the correlation code.

    摘要翻译： 在无线通信系统中的同步处理电路中，相关运算部被设计为具有可重构的并行结构，以提高灵活性，以应对多个无线电系统中的各种同步处理。 无线通信系统中的同步处理电路包括执行相关操作的多个相关运算模块31至3N，每个相关运算模块包括多个相关器60，用于移位相关码的多个移位寄存器50， 将相移代码转移到用于定时相关处理的相邻相关运算单元的接口，以及相关代码选择单元40，其选择用于代码相关处理的外部和单独应用的相关代码和从相邻相关运算单元传送的相关代码作为 相关代码。

    Recording apparatus
    6.
    发明授权
    Recording apparatus 有权
    记录装置

    公开(公告)号：US08608159B2

    公开(公告)日：2013-12-17

    申请号：US13617043

    申请日：2012-09-14

    申请人： Toshiki Takeuchi ,  Haruo Uchida

    发明人： Toshiki Takeuchi ,  Haruo Uchida

    IPC分类号： B65H1/00

    CPC分类号： B65H31/02 ,  B41J13/106 ,  B65H31/20 ,  B65H2405/324 ,  B65H2405/3322 ,  B65H2801/06

    摘要： A recording apparatus includes a cassette having a stacking region for stacking recording materials mounted to main assembly of the recording apparatus; a feeder for feeding the recording material stacked to the cassette; a sheet discharge portion for sheet discharging the recording material having been subjected to a recording operation; a tray movable between a first position where the recording material is incapable of being discharged from the sheet discharge portion and a second position where the recording material is capable of being discharged from a main assembly of the recording apparatus; a holding portion, disposed on the tray, for holding the recording material discharged when the tray is at the second position; an auxiliary portion disposed on the tray and capable of stacking the recording material with the stacking region when the tray is at the second position.

    摘要翻译： 记录装置包括具有用于堆叠安装到记录装置的主组件上的记录材料的堆叠区域的盒; 用于馈送堆叠在盒上的记录材料的馈送器; 用于片材排出已经进行记录操作的记录材料的片材排出部分; 可在第一位置和第二位置之间移动的托盘，其中记录材料不能从纸张排出部分排出，并且记录材料能够从记录装置的主组件排出的第二位置; 保持部，设置在所述托盘上，用于保持当所述托盘处于所述第二位置时排出的所述记录材料; 辅助部分设置在托盘上，并且当托盘处于第二位置时能够将记录材料与堆叠区域堆叠。

    Data transfer device and data transfer method
    10.
    发明授权
    Data transfer device and data transfer method 有权
    数据传输设备和数据传输方式

    公开(公告)号：US08266467B2

    公开(公告)日：2012-09-11

    申请号：US12669508

    申请日：2008-07-24

    申请人： Toshiki Takeuchi

    发明人： Toshiki Takeuchi

    IPC分类号： H04L7/00 ,  G06F13/42

    CPC分类号： G06F13/4291

    摘要： To provide inter-LSI data synchronized transfer with a transfer throughput satisfying a required performance without causing an operation timing difference of the entire system even when a wiring delay between LSIs varies on an evaluation board and an actual device. A master (LSI1) outputs transfer data and a transfer synchronization clock signal to a slave (LSI2). For the edge of a clock signal used for data output at the master (LSI1), the slave (LSI2) latches input data by using a reverse edge. Moreover, upon data transfer from the slave (LSI2) to the master (LSI1), the master (LSI1) selects a latch timing of input data from a plurality of timings so that the transfer time to an internal circuit of the master (LSI1) side is identical regardless of which latch timing is selected.

    摘要翻译： 即使在评估板和实际装置之间的LSI之间的布线延迟变化时，也能够提供满足所需性能的传送吞吐量的LSI间数据同步传送，而不会导致整个系统的操作定时差异。 主机（LSI1）将传送数据和传送同步时钟信号输出到从机（LSI2）。 对于用于在主器件（LSI1）输出的数据的时钟信号的边沿，从器件（LSI2）通过使用反向边沿锁存输入数据。 此外，在从从机（LSI2）到主机（LSI1）的数据传送时，主机（LSI1）从多个定时中选择输入数据的锁存定时，使得到主机（LSI1）的内部电路的传送时间 无论选择哪个锁存定时，一侧是相同的。