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    PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING
    1.
    发明申请
    PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING 审中-公开
    并行操作装置，实现有效的平行运行处理

    公开(公告)号：US20100325386A1

    公开(公告)日：2010-12-23

    申请号：US12821732

    申请日：2010-06-23

    申请人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    发明人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    IPC分类号： G06F15/76

    CPC分类号： G06F9/3879 ,  G06F9/30036 ,  G06F9/3887

    摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

    摘要翻译： 在对应于条目提供的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIMD）指令产生一组控制信号的MIMD指令解码器和存储指定MIMD指令的数据的MIMD寄存器， 提供了一个ALU通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。 可以对每个ALU单元分别执行移动量和操作指令的数据移动和算术/逻辑运算。 因此，在单指令多数据类型处理装置中，可以以灵活的方式高速执行多指令多数据操作。

    Parallel operation device allowing efficient parallel operational processing
    2.
    发明授权
    Parallel operation device allowing efficient parallel operational processing 失效
    并行运行装置允许高效的并行运行处理

    公开(公告)号：US07769980B2

    公开(公告)日：2010-08-03

    申请号：US11840116

    申请日：2007-08-16

    申请人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    发明人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    IPC分类号： G06F15/80

    CPC分类号： G06F9/3879 ,  G06F9/30036 ,  G06F9/3887

    摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction-Multiple Data (MIMD) instruction and an MIMD register storing data designating the MIMD instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit. Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

    摘要翻译： 在对应于条目提供的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIMD）指令产生一组控制信号的MIMD指令解码器和存储指定MIMD指令的数据的MIMD寄存器， 提供了一个ALU通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。 可以对每个ALU单元分别执行移动量和操作指令的数据移动和算术/逻辑运算。 因此，在单指令多数据类型处理装置中，可以以灵活的方式高速执行多指令多数据操作。

    PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING
    3.
    发明申请
    PARALLEL OPERATION DEVICE ALLOWING EFFICIENT PARALLEL OPERATIONAL PROCESSING 失效
    并行操作装置，实现有效的平行运行处理

    公开(公告)号：US20080052497A1

    公开(公告)日：2008-02-28

    申请号：US11840116

    申请日：2007-08-16

    申请人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    发明人： Toshinori Sueyoshi ,  Masahiro Iida ,  Mitsutaka Nakano ,  Fumiaki Senoue ,  Katsuya Mizumoto

    IPC分类号： G06F9/302 ,  G06F9/305

    CPC分类号： G06F9/3879 ,  G06F9/30036 ,  G06F9/3887

    摘要： In arithmetic/logic units (ALU) provided corresponding to entries, an MIMD instruction decoder generating a group of control signals in accordance with a Multiple Instruction Multiple Data (MIME) instruction and an MIMD register storing data designating the MIME instruction are provided, and an inter-ALU communication circuit is provided. The amount and direction of movement of the inter-ALU communication circuit are set by data bits stored in a movement data register. It is possible to execute data movement and arithmetic/logic operation with the amount of movement and operation instruction set individually for each ALU unit Therefore, in a Single Instruction-Multiple Data type processing device, Multiple Instruction-Multiple Data operation can be executed at high speed in a flexible manner.

    摘要翻译： 在对应于条目的算术/逻辑单元（ALU）中，提供根据多指令多数据（MIME）指令产生一组控制信号的MIMD指令解码器和存储指定MIME指令的数据的MIMD寄存器， 提供了ALU间通信电路。 ALU通信电路的移动量和方向由存储在移动数据寄存器中的数据位来设置。 可以通过为每个ALU单元单独设置的移动量和操作指令执行数据移动和算术/逻辑运算。因此，在单指令多数据类型处理装置中，可以在高执行多指令多数据操作 速度灵活。

    Programmable logic circuit device having look up table enabling to reduce implementation area
    5.
    发明授权
    Programmable logic circuit device having look up table enabling to reduce implementation area 失效
    具有查找表的可编程逻辑电路器件能够减少实现面积

    公开(公告)号：US06812737B2

    公开(公告)日：2004-11-02

    申请号：US10183590

    申请日：2002-06-28

    申请人： Toshinori Sueyoshi ,  Masahiro Iida

    发明人： Toshinori Sueyoshi ,  Masahiro Iida

    IPC分类号： H03K19173

    CPC分类号： H03K19/17748 ,  H03K19/17728 ,  H03K19/17784

    摘要： A programmable logic circuit device has a plurality of logic blocks, a plurality of routing wires, a plurality of switch circuits, a plurality of connection blocks, and an I/O block performing an input/output operation with external equipment. The routing wires are connected to each of the logic blocks, the switch circuits are provided at an intersection of each of the routing wires, and the connection blocks are provided between an I/O line of each of the logic blocks and each of the routing wires. Each of the logic blocks has a look up table of M inputs and N outputs, which has a plurality of LUT units; and an internal configuration control circuit controlling an internal configuration of the plurality of LUT units.

    摘要翻译： 可编程逻辑电路器件具有多个逻辑块，多个路由布线，多个开关电路，多个连接块以及与外部设备执行输入/输出操作的I / O块。 路由线连接到每个逻辑块，开关电路设置在每个路由线的交点处，并且连接块设置在每个逻辑块的I / O线和每个路由之间 电线 每个逻辑块具有M个输入和N个输出的查找表，其具有多个LUT单元; 以及控制多个LUT单元的内部配置的内部配置控制电路。