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33 条记录 (耗时 0.013 秒)

    Synchronous serial communication circuit
    1.
    发明授权
    Synchronous serial communication circuit 失效
    同步串行通信电路

    公开(公告)号：US5187720A

    公开(公告)日：1993-02-16

    申请号：US628585

    申请日：1990-12-17

    申请人： Koichi Shibata ,  Toshitaka Fukushima ,  Hiroyuki Watanabe ,  Shinichiro Miyahara ,  Osamu Imagawa

    发明人： Koichi Shibata ,  Toshitaka Fukushima ,  Hiroyuki Watanabe ,  Shinichiro Miyahara ,  Osamu Imagawa

    IPC分类号： H04B5/00 ,  H04B7/26 ,  H04L25/49

    CPC分类号： H04L25/4904

    摘要： The synchronous serial communication circuit transmits and receives data, which is added flag patterns for recognizing the coil winding direction at the first and last of data block, by the electromagnetic induction system using a pair of coils. So, the circuit provides modulation and demodulation circuits acting at the clock of twice of the transfer speed and a flag check circuit for recognizing the inversion of the coil winding direction by judging a state of the flag patterns included in the received data. The transmitted data is converted into the biphase signal by the modulation circuit and is transmitted by driving the coil using the biphase signal. The signal received by the coil is converted into the received data by the demodulation circuit. When the winding directions of coils does not agree, the flag check circuit recognizes the inversion of the coil winding direction and the received data is inverted by the demodulation circuit.

    摘要翻译： 同步串行通信电路通过使用一对线圈的电磁感应系统发送和接收数据，该数据是用于识别数据块的第一和最后的线圈卷绕方向的附加标志模式。 因此，该电路提供作为传送速度的两倍时钟的调制和解调电路，以及通过判断包含在接收数据中的标志模式的状态来识别线圈卷绕方向的反转的标志检查电路。 发送的数据由调制电路转换成双相信号，并通过使用双相信号驱动线圈来发送。 由线圈接收的信号由解调电路转换成接收的数据。 当线圈的绕组方向不一致时，标志检查电路识别线圈卷绕方向的反转，并且接收的数据被解调电路反转。

    Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon
    2.
    发明授权
    Semiconductor wafer-scale integrated device composed of interconnected multiple chips each having an integration circuit chip formed thereon 失效
    半导体晶片级集成器件由互连的多个芯片组成，每个芯片上形成有集成电路芯片

    公开(公告)号：US4907062A

    公开(公告)日：1990-03-06

    申请号：US258112

    申请日：1988-10-14

    申请人： Toshitaka Fukushima

    发明人： Toshitaka Fukushima

    IPC分类号： H01L23/52 ,  H01L21/58 ,  H01L23/538 ,  H01L25/065 ,  H01L27/00

    CPC分类号： H01L24/83 ,  H01L23/538 ,  H01L24/24 ,  H01L24/26 ,  H01L24/82 ,  H01L24/96 ,  H01L25/0655 ,  H01L21/568 ,  H01L2224/04105 ,  H01L2224/2413 ,  H01L2224/24137 ,  H01L2224/45124 ,  H01L2224/48091 ,  H01L2224/8319 ,  H01L2224/8385 ,  H01L2224/92 ,  H01L24/45 ,  H01L24/48 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01014 ,  H01L2924/01018 ,  H01L2924/01042 ,  H01L2924/01074 ,  H01L2924/07802 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/15787

    摘要： A device equivalent to a wafer-scale integrated device is achieved by employing multiple IC chips installed on a silicon wafer. For fabricating the device, conventional IC chips of necessary different types are prepared, having their aluminum-wired surfaces coated with a silicon nitride film. These IC chips are placed on a substrate made of silicon keeping the wired faces face up. The wafer may be provided with depressions in which the chips are placed for precise positioning. Upon these chips and the wafer, a silicon layer is grown by a PVD method. The grown silicon layer fills gaps between the IC chips and binds the chips to each other and to the wafer, forming a single piece of wafer. Excessively grown silicon which is taller than the chips is removed by mechano-chemical polishing until the silicon nitride surfaces are exposed. During this polishing process, the silicon nitride film protects the wired surfaces from mechanical and chemical damage. The silicon nitride film is chemically removed until the aluminum wirings are exposed. An insulating layer and aluminum patterning are formed upon the exposed IC chips and filled gaps to form multi-layer wirings for interconnecting the chips and forming input/output connections. This method allows low cost wafer-scale integration higher density wirings and good heat-removal.

    摘要翻译： 通过使用安装在硅晶片上的多个IC芯片来实现与晶片级集成器件相当的器件。 为了制造该器件，制备必要不同类型的常规IC芯片，其铝线表面涂覆有氮化硅膜。 这些IC芯片放置在由硅制成的基板上，保持有线面朝上。 晶片可以设置有凹部，其中放置芯片用于精确定位。 在这些芯片和晶片上，通过PVD方法生长硅层。 生长的硅层填充IC芯片之间的间隙，并将芯片彼此连接并连接到晶片，形成单片晶片。 通过机械化学抛光除去比芯片高的过度生长的硅，直到暴露氮化硅表面。 在该抛光过程中，氮化硅膜保护有线表面免受机械和化学损伤。 化学去除氮化硅膜直到铝布线露出。 在曝光的IC芯片和填充的间隙上形成绝缘层和铝图案形成以形成用于互连芯片和形成输入/输出连接的多层布线。 该方法允许低成本晶片级集成更高密度的布线和良好的散热。

    Three-state output circuit
    5.
    发明授权
    Three-state output circuit 失效
    三态输出电路

    公开(公告)号：US4322640A

    公开(公告)日：1982-03-30

    申请号：US95073

    申请日：1979-11-16

    申请人： Toshitaka Fukushima ,  Kouji Ueno

    发明人： Toshitaka Fukushima ,  Kouji Ueno

    IPC分类号： G11C17/00 ,  G11C11/41 ,  G11C11/416 ,  G11C17/08 ,  G11C17/14 ,  H01L21/822 ,  H01L27/04 ,  H03K19/018 ,  H03K19/082 ,  H03K19/20

    CPC分类号： G11C17/08 ,  H03K19/01806 ,  H03K19/0826

    摘要： A three-state output circuit is disclosed. The three-state output circuit is comprised of a phase-splitter transistor, a pull-up transistor and a pull-down transistor and further comprised of a control circuit which operates to make the transistors active or non-active. At least one of said transistors is connected to the control circuit via a newly employed PNP transistor through its emitter and base. The collector thereof is connected to a ground point of the three-state output circuit.

    摘要翻译： 公开了一种三态输出电路。 三态输出电路由分相晶体管，上拉晶体管和下拉晶体管组成，并且还包括一个控制电路，其操作以使晶体管工作或非有效。 所述晶体管中的至少一个通过新近采用的PNP晶体管通过其发射极和基极连接到控制电路。 其集电极连接到三态输出电路的接地点。

    Schottky barrier diode clamp transistor
    7.
    发明授权
    Schottky barrier diode clamp transistor 失效
    肖特基势垒二极管钳位晶体管

    公开(公告)号：US4943742A

    公开(公告)日：1990-07-24

    申请号：US333756

    申请日：1989-04-04

    申请人： Toshitaka Fukushima

    发明人： Toshitaka Fukushima

    IPC分类号： H03K19/088 ,  H01L27/06 ,  H01L27/07 ,  H01L29/72 ,  H03K17/04 ,  H03K19/013

    CPC分类号： H01L27/0755 ,  H03K19/013

    摘要： A semiconductor device used for, particularly, an output stage of a logic circuit is formed by a Schottky.barrier.diode clamping transistor. A clamping circuit is provided between a collector and a base for clamping a collector potential. The clamping circuit is formed by a Schottky.barrier.diode (SBD) and a series connected resistance coupled to the Schottky.barrier.diode. A collector resistance is divided by resistance division using the series resistance (FIG. 6).

    摘要翻译： 用于特别是逻辑电路的输出级的半导体器件由肖特基二极管钳位晶体管形成。 钳位电路设置在集电极和基极之间，用于钳位集电极电位。 钳位电路由肖特基二极管（SBD）和耦合到肖特基二极管的串联电阻形成。 集电极电阻用电阻分割除以串联电阻（图6）。

    Method of forming groove isolation filled with dielectric for semiconductor device
    8.
    发明授权
    Method of forming groove isolation filled with dielectric for semiconductor device 失效
    形成用于半导体器件的电介质填充槽隔离的方法

    公开(公告)号：US4866004A

    公开(公告)日：1989-09-12

    申请号：US236319

    申请日：1988-08-25

    申请人： Toshitaka Fukushima

    发明人： Toshitaka Fukushima

    IPC分类号： H01L21/76 ,  H01L21/308 ,  H01L21/763 ,  H01L29/00

    CPC分类号： H01L21/763 ,  H01L21/308

    摘要： In manufacturing processes of an integrated circuit, isolation technology between adjacent active elements on a substrate plays an important role. Groove isolation filled with dielectric is known as an effective way of achieving a high integration density, however the prior art methods of forming the isolation groove have the problem of formation of BIRD'S HEAD or BIRD'S BEAK portions around the isolation region, which restricts the integration density and deteriorates a flatness of the substrate. The method of forming isolation groove according to the present invention discloses that the method comprising the steps of removing a silicon oxide layer on a specified region surrounding the isolation groove, and depositing a silicon nitride layer directly on the substrate and forming the groove self-aligned using the above silicon oxide layer removal process, eliminates the above mentioned problems achieving a higher density of integration, a flatness of the substrate and improvement of the integrated circuit.

    摘要翻译： 在集成电路的制造过程中，衬底上的相邻有源元件之间的隔离技术起着重要的作用。 作为实现高集成密度的有效方式，已知填充有电介质的沟槽隔离物，然而形成隔离槽的现有技术方法存在在隔离区域周围形成BIRD'S HEAD或BIRD'S BEAK部分的问题，这限制了集成密度 并使基板的平坦度变差。 根据本发明的形成隔离槽的方法公开了该方法包括以下步骤：在隔离槽周围的特定区域上去除氧化硅层，并将氮化硅层直接沉积在衬底上并形成沟槽自对准 使用上述氧化硅层去除工艺，消除了实现更高的集成密度，基板的平坦度和集成电路的改进的上述问题。

    Data collection system having stationary unit with electromagnetic induction circuitry for bidirectionally relaying data
    9.
    发明授权
    Data collection system having stationary unit with electromagnetic induction circuitry for bidirectionally relaying data 失效
    数据采集​​系统具有带电磁感应电路的固定单元，用于双向中继数据

    公开(公告)号：US4839854A

    公开(公告)日：1989-06-13

    申请号：US907401

    申请日：1986-09-12

    申请人： Yasuo Sakami ,  Shigetaka Okina ,  Junichi Tsubouchi ,  Shozo Izaki ,  Toshitaka Fukushima ,  Hiroyuki Watanabe ,  Masao Ishizaki

    发明人： Yasuo Sakami ,  Shigetaka Okina ,  Junichi Tsubouchi ,  Shozo Izaki ,  Toshitaka Fukushima ,  Hiroyuki Watanabe ,  Masao Ishizaki

    IPC分类号： G06F17/40

    CPC分类号： G06F3/0231 ,  G06F1/1632 ,  G06F3/023 ,  H04Q9/00 ,  G08C2201/93 ,  H04Q2209/50

    摘要： A system for collection of data and entry of the data to a host computer has a portable, hand held, data collector for collecting data and a stationary data relay for receiving the data from the data collector and for transmitting the data to the host computer. The portable hand held data collector includes a case of a size and shape to be held by one hand during use, a keyboard for inputting the data, displaying for displaying the data, memory for storing the data and an interface for transmitting the data to external. The data relay includes a case shaped to set the portable data collector thereon, of first interface for receiving the data transmitted from the data collector and of said interface for comunicating bidirectionally to the host computer.

    摘要翻译： 用于收集数据并将数据输入到主计算机的系统具有用于收集数据的便携式手持式数据收集器和用于从数据收集器接收数据并将数据发送到主计算机的固定数据中继器。 便携式手持式数据收集器包括在使用期间由一只手保持的尺寸和形状的壳体，用于输入数据的键盘，用于显示数据的显示，用于存储数据的存储器和用于将数据发送到外部的接口 。 该数据继电器包括用于设置便携式数据收集器的壳体，用于接收从数据采集器发送的数据的第一接口和用于与主计算机双向通信的所述接口。

    Field programmable device with circuitry for detecting poor insulation between adjacent word lines
    10.
    发明授权
    Field programmable device with circuitry for detecting poor insulation between adjacent word lines 失效
    具有用于检测相邻字线之间绝缘不良的电路的现场可编程器件

    公开(公告)号：US4459694A

    公开(公告)日：1984-07-10

    申请号：US333653

    申请日：1981-12-23

    申请人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    发明人： Kouji Ueno ,  Toshitaka Fukushima ,  Kazumi Koyama

    IPC分类号： G11C29/00 ,  G11C17/00 ,  G11C29/04 ,  G11C29/24 ,  H01L21/66 ,  H01L21/822 ,  H01L21/8229 ,  H01L27/04 ,  H01L27/102 ,  G06F11/22

    CPC分类号： G11C29/24 ,  G11C29/04

    摘要： A field programmable device comprises regular word lines, regular bit lines, regular memory cells connected at the intersections of the regular word lines and the regular bit lines, at least one test word line adjacent to one of the regular bit lines, and alternately arranged conducting and nonconducting test memory cells arranged at the intersections of the test bit lines and the regular word lines. According to the invention, for the purpose of determining poor insulation between the word lines, the test bit line and the regular word line are insulated by an insulating layer in each nonconducting test memory cell.

    摘要翻译： 现场可编程设备包括常规字线，规则位线，连接在正常字线和规则位线的交点处的常规存储器单元，至少一个与常规位线之一相邻的测试字线，并且交替排列导电 以及布置在测试位线和常规字线的交点处的非导体测试存储单元。 根据本发明，为了确定字线之间的差的绝缘，测试位线和常规字线在每个非导通测试存储单元中被绝缘层绝缘。