公开(公告)号：US08330203B2

公开(公告)日：2012-12-11

申请号：US12507473

申请日：2009-07-22

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L29/76 ,  H01L29/788

CPC分类号： H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： A first insulation film is formed on a semiconductor substrate. A first gate electrode is formed on the first insulation film. A second insulation film is formed on an upper surface and a side surface of the first gate electrode. A second gate electrode is formed on the second insulation film. The entirety of that part of the second gate electrode, which is located above the second insulation film formed on the upper surface of the first gate electrode, is a silicide layer. At least a portion of that part of the second gate electrode, which is located on the side surface of the first gate electrode, is a silicon layer.

摘要翻译： 第一绝缘膜形成在半导体衬底上。 在第一绝缘膜上形成第一栅电极。 在第一栅电极的上表面和侧表面上形成第二绝缘膜。 在第二绝缘膜上形成第二栅电极。 第二栅电极的位于第一栅电极的上表面上形成的第二绝缘膜上方的整个部分是硅化物层。 位于第一栅电极的侧表面上的第二栅电极的该部分的至少一部分是硅层。

公开(公告)号：US08258568B2

公开(公告)日：2012-09-04

申请号：US13044102

申请日：2011-03-09

申请人： Toshitake Yaegashi ,  Junichi Shiozawa

发明人： Toshitake Yaegashi ,  Junichi Shiozawa

IPC分类号： H01L29/788

CPC分类号： H01L29/78 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11529

摘要： A first isolation is formed on a semiconductor substrate, and a first element region is isolated via the first isolation. A first gate insulating film is formed on the first element region, and a first gate electrode is formed on the first gate insulating film. A second isolation is formed on the semiconductor substrate, and a second element region is isolated via the second isolation. A second gate insulating film is formed on the second element region, and a second gate electrode is formed on the second gate insulating film. A first oxide film is formed between the first isolation and the first element region. A second oxide film is formed between the second isolation and the second element region. The first isolation has a width narrower than the second isolation, and the first oxide film has a thickness thinner than the second oxide film.

摘要翻译： 第一隔离形成在半导体衬底上，第一元件区通过第一隔离隔离。 第一栅绝缘膜形成在第一元件区上，第一栅电极形成在第一栅极绝缘膜上。 第二隔离形成在半导体衬底上，第二元件区通过第二隔离隔离。 第二栅极绝缘膜形成在第二元件区域上，第二栅电极形成在第二栅极绝缘膜上。 在第一隔离和第一元件区之间形成第一氧化膜。 在第二隔离和第二元件区之间形成第二氧化膜。 第一隔离物的宽度比第二隔离宽，第一氧化膜的厚度比第二氧化膜薄。

公开(公告)号：US08217468B2

公开(公告)日：2012-07-10

申请号：US13112769

申请日：2011-05-20

申请人： Toshitake Yaegashi ,  Koki Ueno

发明人： Toshitake Yaegashi ,  Koki Ueno

IPC分类号： H01L29/76

CPC分类号： H01L21/823481 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524

摘要： In device isolation trenches, a first device-isolation insulator film is formed to have recesses thereon and a second device-isolation insulator film is formed in the recesses. The uppermost portions at both ends of the first device-isolation insulator film are located higher than the uppermost portions at both ends of the second device-isolation insulator film.

摘要翻译： 在器件隔离沟槽中，第一器件隔离绝缘膜形成为具有凹槽，并且在凹部中形成第二器件隔离绝缘膜。 第一器件隔离绝缘膜的两端的最上部位于比第二器件隔离绝缘膜的两端的最上部更高位置。

公开(公告)号：US20120032251A1

公开(公告)日：2012-02-09

申请号：US13275014

申请日：2011-10-17

申请人： Toshitake YAEGASHI

发明人： Toshitake YAEGASHI

IPC分类号： H01L29/792

CPC分类号： H01L27/1157 ,  H01L27/11565 ,  H01L27/11568 ,  H01L29/1041 ,  H01L29/105 ,  H01L29/513 ,  H01L29/78

摘要： First and second memory cells have first and second channels, first and second tunnel insulating films, first and second charge storage layers formed of an insulating film, first and second block insulating films, and first and second gate electrodes. A first select transistor has a third channel, a first gate insulating film, and a first gate electrode. The first channel includes a first-conductivity-type region and a second-conductivity-type region which is formed on at least a part of the first-conductivity-type region and whose conductivity type is opposite to the first conductivity type. The third channel includes the first-conductivity-type region and the second-conductivity-type region formed on the first-conductivity-type region. The number of data stored in the first memory cell is smaller than that of data stored in the second memory cell.

摘要翻译： 第一和第二存储单元具有第一和第二通道，第一和第二隧道绝缘膜，由绝缘膜，第一和第二块绝缘膜以及第一和第二栅电极形成的第一和第二电荷存储层。 第一选择晶体管具有第三沟道，第一栅极绝缘膜和第一栅极电极。 第一通道包括形成在第一导电型区域的至少一部分上并且其导电类型与第一导电类型相反的第一导电型区域和第二导电型区域。 第三通道包括形成在第一导电型区域上的第一导电型区域和第二导电型区域。 存储在第一存储器单元中的数据的数量小于存储在第二存储器单元中的数据的数量。

公开(公告)号：US20110298031A1

公开(公告)日：2011-12-08

申请号：US13213597

申请日：2011-08-19

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L29/788

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324

摘要： A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

摘要翻译： 半导体存储器件包括第一选择晶体管，第一阶梯部分和第一接触插头。 第一选择晶体管形成在衬底的上表面的一侧，并且具有第一多层栅极。 第一台阶部分通过蚀刻与第一选择晶体管的第一多层栅极相邻的衬底形成，使得第一阶梯部分在衬底的上表面中形成空腔。 第一接触插塞形成在第一阶梯部分中。

公开(公告)号：US20110175155A1

公开(公告)日：2011-07-21

申请号：US12881730

申请日：2010-09-14

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L29/792

CPC分类号： H01L27/11568 ,  H01L27/11582 ,  H01L29/40117 ,  H01L29/4234 ,  H01L29/792

摘要： In one embodiment, a nonvolatile semiconductor memory device includes a plurality of memory cell transistors disposed on device regions. Each of the memory cell transistors includes a tunnel insulator disposed on a device region, a charge storage layer disposed on the tunnel insulator, and formed of an insulator, a block insulator disposed on the charge storage layer, and a gate electrode disposed on the block insulator. The gate electrode of each memory cell transistor is isolated by an insulator from the gate electrode of an adjacent memory cell transistor adjacent in a gate length direction. Further, the block insulator is disposed on the device region extending in the gate length direction, and continuously disposed in regions under the gate electrodes of the memory cell transistors and in regions between the gate electrodes of the memory cell transistors. Further, the block insulator disposed in the regions between the gate electrodes includes a thin portion which has a smaller thickness than the block insulator formed in the regions under the gate electrodes.

摘要翻译： 在一个实施例中，非易失性半导体存储器件包括设置在器件区域上的多个存储单元晶体管。 每个存储单元晶体管包括设置在器件区域上的隧道绝缘体，设置在隧道绝缘体上的电荷存储层，并且由绝缘体，设置在电荷存储层上的块绝缘体和设置在该块上的栅电极 绝缘子。 每个存储单元晶体管的栅电极由与栅极长度方向相邻的相邻存储单元晶体管的栅极的绝缘体隔离。 此外，块绝缘体设置在沿栅极长度方向延伸的器件区域上，并且连续地设置在存储单元晶体管的栅电极下方的区域中以及存储单元晶体管的栅电极之间的区域中。 此外，设置在栅电极之间的区域中的块绝缘体包括具有比形成在栅电极下方的区域中的块绝缘体更小的厚度的薄部。

公开(公告)号：US20110108905A1

公开(公告)日：2011-05-12

申请号：US13007258

申请日：2011-01-14

申请人： Masayuki ICHIGE ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

发明人： Masayuki ICHIGE ,  Fumitaka Arai ,  Riichiro Shirota ,  Toshitake Yaegashi ,  Yoshio Ozawa ,  Akihito Yamamoto ,  Ichiro Mizushima ,  Yoshihiko Saito

IPC分类号： H01L29/788

CPC分类号： H01L29/42336 ,  H01L21/28273 ,  H01L27/0207 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/42324 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory includes first and second memory cells having a floating gate and a control gate. The floating gate of the first and second memory cells is comprised a first part, and a second part arranged on the first part, and a width of the second part in an extending direction of the control gate is narrower than that of the first part. A first space between the first parts of the first and second memory cells is filled with one kind of an insulator. The control gate is arranged at a second space between the second parts of the first and second memory cells.

摘要翻译： 非易失性半导体存储器包括具有浮动栅极和控制栅极的第一和第二存储单元。 第一和第二存储单元的浮动栅极包括第一部分和布置在第一部分上的第二部分，并且第二部分在控制栅极的延伸方向上的宽度比第一部分的宽度窄。 第一和第二存储单元的第一部分之间的第一空间填充有一种绝缘体。 控制栅极被布置在第一和第二存储单元的第二部分之间的第二空间处。

公开(公告)号：US07928497B2

公开(公告)日：2011-04-19

申请号：US11854845

申请日：2007-09-13

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L29/788

CPC分类号： H01L29/513 ,  G11C16/0466 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11543

摘要： A nonvolatile semiconductor memory according to examples of the present invention comprises a memory cell and a peripheral transistor. The memory cell has a first intergate insulating film having a multilayer structure and provided on a floating gate electrode and an isolation insulating layer. The peripheral transistor has a second intergate insulating film having a multilayer structure and provided on a first gate electrode and a second isolation insulating layer. The first and second intergate insulating films have the same structure, and a lowermost insulating layer of the first intergate insulating film on the first isolation insulating layer is thinner than a lowermost insulating layer of the second intergate insulating film on the second isolation insulating layer.

摘要翻译： 根据本发明实施例的非易失性半导体存储器包括存储单元和外围晶体管。 存储单元具有具有多层结构并设置在浮栅电极和隔离绝缘层上的第一隔间绝缘膜。 外围晶体管具有第二栅极间绝缘膜，具有多层结构并且设置在第一栅电极和第二隔离绝缘层上。 第一和第二隔间绝缘膜具有相同的结构，并且第一隔离绝缘层上的第一隔间绝缘膜的最下层绝缘层比第二隔离绝缘层上的第二隔间绝缘膜的最下层绝缘层薄。

公开(公告)号：US07842993B2

公开(公告)日：2010-11-30

申请号：US12538469

申请日：2009-08-10

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L29/788

CPC分类号： H01L27/11565 ,  H01L21/28282 ,  H01L27/11568

摘要： First and second memory cell transistors are isolated by an element isolation insulating film. A barrier insulating film covers the element isolation insulating film. The first memory cell transistor includes a first tunnel insulating film, a first charge storage layer made of an insulating film, a first block insulating film, and a first gate electrode. The second memory cell transistor includes a second tunnel insulating film, a second charge storage layer made of an insulating film, a second block insulating film, and a second gate electrode. The barrier insulating film is in contact with the first and second charge storage layers, and has a film thickness smaller than that of the first and second charge storage layers.

摘要翻译： 第一和第二存储单元晶体管被元件隔离绝缘膜隔离。 隔离绝缘膜覆盖元件隔离绝缘膜。 第一存储单元晶体管包括第一隧道绝缘膜，由绝缘膜制成的第一电荷存储层，第一块绝缘膜和第一栅电极。 第二存储单元晶体管包括第二隧道绝缘膜，由绝缘膜制成的第二电荷存储层，第二块绝缘膜和第二栅电极。 阻挡绝缘膜与第一和第二电荷存储层接触，并且具有比第一和第二电荷存储层的膜厚小的膜厚度。

公开(公告)号：US07812386B2

公开(公告)日：2010-10-12

申请号：US12246864

申请日：2008-10-07

申请人： Toshitake Yaegashi

发明人： Toshitake Yaegashi

IPC分类号： H01L27/108 ,  H01L29/76 ,  H01L29/94 ,  H01L31/119

CPC分类号： H01L27/115 ,  H01L21/28273 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11526 ,  H01L27/11529 ,  H01L29/42324

摘要： A semiconductor memory device includes a first select transistor, first stepped portion, and a first contact plug. The first select transistor is formed on a side of an upper surface of a substrate and has a first multi-layer gate. The first stepped portion is formed by etching the substrate adjacent to the first multi-layer gate of the first select transistor such that the first stepped portion forms a cavity in the upper surface of the substrate. The first contact plug is formed in the first stepped portion.

摘要翻译： 半导体存储器件包括第一选择晶体管，第一阶梯部分和第一接触插头。 第一选择晶体管形成在衬底的上表面的一侧，并且具有第一多层栅极。 第一台阶部分通过蚀刻与第一选择晶体管的第一多层栅极相邻的衬底形成，使得第一阶梯部分在衬底的上表面中形成空腔。 第一接触插塞形成在第一阶梯部分中。