公开(公告)号：US08518760B2

公开(公告)日：2013-08-27

申请号：US13050117

申请日：2011-03-17

申请人： Shunpei Yamazaki ,  Osamu Nakamura ,  Shinji Maekawa ,  Gen Fujii ,  Toshiyuki Isa

发明人： Shunpei Yamazaki ,  Osamu Nakamura ,  Shinji Maekawa ,  Gen Fujii ,  Toshiyuki Isa

IPC分类号： H01L21/84

CPC分类号： H01L51/0022 ,  G09G3/3208 ,  G09G3/3225 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/3244 ,  H01L51/055 ,  H01L51/529

摘要： The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

摘要翻译： 本发明提供一种显示装置及其制造方法，其通过有效地增加材料以及简化步骤来制造。 此外，本发明提供了一种用于形成用于形成显示装置的布线等图案以具有优异的可控性的预定形状的技术。 制造显示装置的方法包括以下步骤：形成疏液区域; 选择性地将激光束照射在疏液区域以形成亲液性区域; 选择性地将含有导电材料的组合物在亲液区域中排出以形成栅极电极层; 在栅电极层上形成栅极绝缘层和半导体层; 在半导体层上排出含有导电材料的组合物，以形成源电极层和漏电极层; 以及在源极或漏极电极层上形成像素电极层。

公开(公告)号：US08513664B2

公开(公告)日：2013-08-20

申请号：US12490458

申请日：2009-06-24

申请人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki

发明人： Toshiyuki Isa ,  Yasuhiro Jinbo ,  Sachiaki Tezuka ,  Koji Dairiki ,  Hidekazu Miyairi ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L31/00

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78696

摘要： A thin film transistor includes, as a buffer layer, an amorphous semiconductor layer having nitrogen or an NH group between a gate insulating layer and source and drain regions and at least on the source and drain regions side. As compared to a thin film transistor in which an amorphous semiconductor is included in a channel formation region, on-current of a thin film transistor can be increased. In addition, as compared to a thin film transistor in which a microcrystalline semiconductor is included in a channel formation region, off-current of a thin film transistor can be reduced.

摘要翻译： 薄膜晶体管包括作为缓冲层的至少在源极和漏极区域上具有氮或NH基的非晶半导体层，栅极绝缘层与源极和漏极区之间。 与在沟道形成区域中包含非晶半导体的薄膜晶体管相比，可以提高薄膜晶体管的导通电流。 此外，与在沟道形成区域中包含微晶半导体的薄膜晶体管相比，可以减小薄膜晶体管的截止电流。

公开(公告)号：US07993991B2

公开(公告)日：2011-08-09

申请号：US12326661

申请日：2008-12-02

申请人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

发明人： Hidekazu Miyairi ,  Shigeki Komori ,  Toshiyuki Isa ,  Ryu Komatsu

IPC分类号： H01L21/00 ,  G02F1/136

CPC分类号： H01L27/1288 ,  H01L27/1214 ,  H01L29/42384 ,  H01L29/4908 ,  H01L29/78609

摘要： A manufacturing method of a thin film transistor and a display device using a small number of masks is provided. A first conductive film, an insulating film, a semiconductor film, an impurity semiconductor film, and a second conductive film are stacked. Then, a resist mask having a recessed portion is formed thereover using a multi-tone mask. First etching is performed to form a thin-film stack body, and second etching in which the thin-film stack body is side-etched is performed to form a gate electrode layer. The resist is made to recede, and then, a source electrode, a drain electrode, and the like are formed; accordingly, a thin film transistor is manufactured.

摘要翻译： 提供了薄膜晶体管的制造方法和使用少量掩模的显示装置。 堆叠第一导电膜，绝缘膜，半导体膜，杂质半导体膜和第二导电膜。 然后，使用多色调掩模在其上形成具有凹部的抗蚀剂掩模。 进行第一蚀刻以形成薄膜堆叠体，并且进行薄膜叠层体被侧蚀刻的第二蚀刻以形成栅极电极层。 使抗蚀剂后退，然后形成源电极，漏电极等; 因此，制造薄膜晶体管。

公开(公告)号：US20110121300A1

公开(公告)日：2011-05-26

申请号：US12948251

申请日：2010-11-17

申请人： Hidekazu Miyairi ,  Toshiyuki Isa

发明人： Hidekazu Miyairi ,  Toshiyuki Isa

IPC分类号： H01L33/16

CPC分类号： H01L27/1251 ,  H01L27/1233 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/78648 ,  H01L29/78696

摘要： An object is to provide a display device whose frame can be narrowed and whose display characteristics are excellent. The display device includes a driver circuit and a pixel portion. The driver circuit and the pixel portion are formed using a dual-gate thin film transistor and a single-gate thin film transistor, respectively. In the dual-gate thin film transistor in the display device, a semiconductor layer is formed using a microcrystalline semiconductor region and a pair of amorphous semiconductor regions, and a gate insulating layer and an insulating layer are in contact with the microcrystalline semiconductor region of the semiconductor layer.

摘要翻译： 目的在于提供一种可以缩小框架的显示装置，其显示特性优异的显示装置。 显示装置包括驱动电路和像素部分。 驱动器电路和像素部分分别使用双栅极薄膜晶体管和单栅极薄膜晶体管形成。 在显示装置中的双栅极薄膜晶体管中，使用微晶半导体区域和一对非晶半导体区域形成半导体层，并且栅极绝缘层和绝缘层与微晶半导体区域的微晶半导体区域接触 半导体层。

公开(公告)号：US07939888B2

公开(公告)日：2011-05-10

申请号：US11857729

申请日：2007-09-19

申请人： Shunpei Yamazaki ,  Osamu Nakamura ,  Shinji Maekawa ,  Gen Fujii ,  Toshiyuki Isa

发明人： Shunpei Yamazaki ,  Osamu Nakamura ,  Shinji Maekawa ,  Gen Fujii ,  Toshiyuki Isa

IPC分类号： H01L27/01 ,  H01L27/12 ,  H01L31/0392

CPC分类号： H01L51/0022 ,  G09G3/3208 ,  G09G3/3225 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/3244 ,  H01L51/055 ,  H01L51/529

摘要： The invention provides a display device and a method for manufacturing thereof by increasing a material efficiently as well as simplifying steps. Also, the invention provides a technique for forming a pattern such as a wiring, that is used for forming a display device, to have a predetermined shape with an excellent controllability. The method for manufacturing a display device includes the steps of: forming a lyophobic region; selectively irradiating laser beam in the lyophobic region to form a lyophilic region; selectively discharging a composition, that contains a conductive material, in the lyophilic region to form a gate electrode layer; forming a gate insulating layer and a semiconductor layer over the gate electrode layer; discharging a composition containing a conductive material over the semiconductor layer to form a source electrode layer and a drain electrode layer; and forming a pixel electrode layer on the source or drain electrode layer.

摘要翻译： 本发明提供一种显示装置及其制造方法，其通过有效地增加材料以及简化步骤来制造。 此外，本发明提供了一种用于形成用于形成显示装置的布线等图案以具有优异的可控性的预定形状的技术。 制造显示装置的方法包括以下步骤：形成疏液区域; 选择性地将激光束照射在疏液区域以形成亲液性区域; 选择性地将含有导电材料的组合物在亲液区域中排出以形成栅极电极层; 在栅电极层上形成栅极绝缘层和半导体层; 在半导体层上排出含有导电材料的组合物，以形成源电极层和漏电极层; 以及在源极或漏极电极层上形成像素电极层。

公开(公告)号：US07768009B2

公开(公告)日：2010-08-03

申请号：US12196798

申请日：2008-08-22

申请人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Satoshi Kobayashi ,  Ikuko Kawamata ,  Koji Dairiki ,  Shigeki Komori ,  Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L29/04 ,  H01L29/10 ,  H01L27/12

CPC分类号： H01L29/04 ,  H01L29/41733 ,  H01L29/4908 ,  H01L29/66765 ,  H01L29/78696

摘要： A display device including a thin film transistor with high electric characteristics and high reliability, and a method for manufacturing the display device with high mass-productivity. In a display device including an inverted-staggered channel-stop-type thin film transistor, the inverted-staggered channel-stop-type thin film transistor includes a microcrystalline semiconductor film including a channel formation region, and an impurity region containing an impurity element of one conductivity type is selectively provided in a region which is not overlapped with source and drain electrodes, in the channel formation region of the microcrystalline semiconductor film.

摘要翻译： 一种包括具有高电特性和高可靠性的薄膜晶体管的显示装置，以及具有高批量生产率的显示装置的制造方法。 在包括反交错通道停止型薄膜晶体管的显示装置中，反交错通道停止型薄膜晶体管包括包含沟道形成区的微晶半导体膜，以及含有杂质元素的杂质区 在微晶半导体膜的沟道形成区域中，在不与源极和漏极重叠的区域中选择性地提供一种导电型。

公开(公告)号：US20100136782A1

公开(公告)日：2010-06-03

申请号：US12699984

申请日：2010-02-04

申请人： Toshiyuki ISA ,  Shunpei YAMAZAKI

发明人： Toshiyuki ISA ,  Shunpei YAMAZAKI

IPC分类号： H01L21/768

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/7688 ,  H01L23/5222 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film).

摘要翻译： 在半导体器件的制造工艺中，电镀和CMP已经出现了用于形成布线的制造成本增加的问题。 相应地，在其上形成掩模之后，在多孔绝缘膜中形成开口，并且含有Ag的导电材料落入开口中。 此外，通过用激光的选择性照射烘烤落入开口中的导电材料，形成第一导电层。 随后，通过溅射在整个表面上形成金属膜，之后除去掩模，仅使金属膜保留在第一导电层上，从而形成嵌入的布线层，该布线层由含有Ag的第一导电层 和第二导电层（金属膜）。

公开(公告)号：US07696625B2

公开(公告)日：2010-04-13

申请号：US11283876

申请日：2005-11-22

申请人： Toshiyuki Isa ,  Shunpei Yamazaki

发明人： Toshiyuki Isa ,  Shunpei Yamazaki

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L21/76877 ,  H01L21/288 ,  H01L21/76843 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76862 ,  H01L21/76864 ,  H01L21/76874 ,  H01L21/7688 ,  H01L23/5222 ,  H01L23/53242 ,  H01L23/53252 ,  H01L23/5329 ,  H01L24/45 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73265 ,  H01L2924/12044 ,  H01L2924/14 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/00

摘要： In a manufacturing process of a semiconductor device, electroplating and CMP have had a problem of increase in manufacturing costs for forming a wiring. Correspondingly, an opening is formed in a porous insulating film after a mask is formed thereover, and a conductive material containing Ag is dropped into the opening. Further, a first conductive layer is formed by baking the conductive material dropped into the opening by selective irradiation with laser light. Subsequently, a metal film is formed over the entire surface by sputtering, and the mask is removed thereafter to have only the metal film remain over the first conductive layer, thereby forming an embedded wiring layer formed with a stack of the first conductive layer containing Ag and the second conductive layer (metal film).

摘要翻译： 在半导体器件的制造工艺中，电镀和CMP已经出现了用于形成布线的制造成本增加的问题。 相应地，在其上形成掩模之后，在多孔绝缘膜中形成开口，并且含有Ag的导电材料落入开口中。 此外，通过用激光的选择性照射烘烤落入开口中的导电材料，形成第一导电层。 随后，通过溅射在整个表面上形成金属膜，然后除去掩模，使得只有金属膜保留在第一导电层上，从而形成嵌入布线层，该布线层由含有Ag的第一导电层 和第二导电层（金属膜）。

公开(公告)号：US07635889B2

公开(公告)日：2009-12-22

申请号：US11333701

申请日：2006-01-17

申请人： Toshiyuki Isa ,  Gen Fujii ,  Masafumi Morisue ,  Ikuko Kawamata

发明人： Toshiyuki Isa ,  Gen Fujii ,  Masafumi Morisue ,  Ikuko Kawamata

IPC分类号： H01L23/48

CPC分类号： H01L21/288 ,  H01L21/02672 ,  H01L21/76838 ,  H01L27/12 ,  H01L27/124 ,  H01L27/1285 ,  H01L27/1292 ,  H01L27/3248 ,  H01L27/3276 ,  H01L51/0019 ,  H01L51/0022 ,  H01L51/0023 ,  H01L2924/0002 ,  Y02P80/30 ,  H01L2924/00

摘要： Conductive layers having knots are adjacently formed with uniform distance therebetween. Droplets of the conductive layers are discharged to stagger centers of the droplets in a length direction of wirings so that the centers of the discharged droplets are not on the same line in a line width direction between the adjacent conductive layers. Since the centers of the droplets are staggered, parts of the conductive layers each having a widest line width (the widest width of knot) are not connected to each other, and the conductive layers can be formed adjacently with a shorter distance therebetween.

摘要翻译： 具有结的导电层相邻地形成，其间具有均匀的距离。 导电层的液滴在布线的长度方向上被排出到液滴的错开中心，使得排出的液滴的中心在相邻导电层之间的线宽方向上不在相同的线上。 由于液滴的中心是错开的，所以每个具有最宽的线宽（结的最宽的宽度）的导电层的部分彼此不连接，导电层可以以较短的距离相邻地形成。

公开(公告)号：US20090267068A1

公开(公告)日：2009-10-29

申请号：US12429486

申请日：2009-04-24

申请人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

发明人： Koji DAIRIKI ,  Hidekazu MIYAIRI ,  Toshiyuki ISA ,  Akiharu MIYANAGA ,  Takuya HIROHASHI ,  Shunpei YAMAZAKI ,  Takeyoshi WATABE

IPC分类号： H01L29/786

CPC分类号： H01L27/127 ,  H01J37/32091 ,  H01L27/1214 ,  H01L27/1218 ,  H01L27/1288 ,  H01L29/04 ,  H01L29/66765 ,  H01L29/78669 ,  H01L29/78678 ,  H01L29/78696

摘要： The thin film transistor includes a gate insulating layer covering a gate electrode, over a substrate having an insulating surface; a semiconductor layer forming a channel formation region, in which a plurality of crystal regions is included in an amorphous structure; an impurity semiconductor layer imparting one conductivity type which forms a source region and a drain region; and a buffer layer formed from an amorphous semiconductor, which is located between the semiconductor layer and the impurity semiconductor layer. The thin film transistor includes the crystal region which includes minute crystal grains and inverted conical or inverted pyramidal grain each of which grows approximately radially from a position away from an interface between the gate insulating layer and the semiconductor layer toward a direction in which the semiconductor layer is deposited in a region which does not reach the impurity semiconductor layer.

摘要翻译： 薄膜晶体管包括覆盖栅电极的栅极绝缘层，在具有绝缘表面的基板上; 形成在非晶结构中包含多个晶体区域的沟道形成区域的半导体层; 赋予形成源极区域和漏极区域的一种导电型的杂质半导体层; 以及由位于半导体层和杂质半导体层之间的非晶半导体形成的缓冲层。 薄膜晶体管包括晶体区域，其包括微小晶粒和倒圆锥形或倒棱锥晶粒，其每个从远离栅极绝缘层和半导体层之间的界面的位置朝向半导体层的方向大致径向地生长 沉积在不到达杂质半导体层的区域中。