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公开(公告)号：US07853918B2
公开(公告)日：2010-12-14
申请号：US12013999
申请日：2008-01-14
Applicant: Jiing-Shin Shyu , Tseng Chin Lo
Inventor： Jiing-Shin Shyu , Tseng Chin Lo
Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.
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公开(公告)号：US07782073B2
公开(公告)日：2010-08-24
申请号：US11731444
申请日：2007-03-30
Applicant: Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
Inventor： Tseng Chin Lo , Kuo-Tsai Li , Shien-Yang Wu
IPC: G01R31/26
CPC classification number: G01R31/2884 , G01R31/2831 , G01R31/2891 , H01L2924/0002 , H01L2924/00
Abstract: A testline structure made for integrated circuit tests is presented. The structure includes an array of testline pads formed in the scribe line area or integrated circuit die area on a semiconductor substrate, a plurality of test devices formed under the pads area, and a select circuit selectively connecting one of the test devices. The testline structure of this invention enables access to a large number of test devices through the same number of pads as on a conventional testline and can be employed to conduct parametric, reliability, and functional tests on the same. A source measurement unit (SMU) in a conventional integrated circuit tester is employed to sense and force predetermined test conditions on the test device terminals and conduct accurate Kelvin tests on the selected device. A method of using this testline structure is also presented.
Abstract translation: 介绍了用于集成电路测试的测试线结构。 该结构包括形成在半导体衬底上的划线区域或集成电路管芯区域中的测试线焊盘阵列，形成在焊盘区域下方的多个测试设备以及选择性地连接其中一个测试设备的选择电路。 本发明的测试线结构能够通过与常规测试线上相同数量的焊盘来访问大量的测试设备，并且可以用它来进行参数，可靠性和功能测试。 采用常规集成电路测试仪中的源测量单元（SMU）来感测和强制测试设备端子上的预定测试条件，并在所选设备上进行准确的开尔文测试。 还提出了使用该测试线结构的方法。
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公开(公告)号：US20090181314A1
公开(公告)日：2009-07-16
申请号：US12013999
申请日：2008-01-14
Applicant: Jiing-Shin Shyu , Tseng Chin Lo
Inventor： Jiing-Shin Shyu , Tseng Chin Lo
CPC classification number: G03F1/36 , G03F1/80 , H01L27/0203
Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.
Abstract translation: 插入虚拟图案的方法包括提供包括主图案的窗口区域。 主图案包括第一类型特征的第一图案和第二类型特征的第二图案。 第一类和第二类是不同类型。 该方法还包括在整个窗口区域全局地插入第一虚拟图案，其中第一伪图案是第一类型特征的虚拟图案; 扩大主图案以产生放大的主图案，其中放大的主图案占据窗口区域的扩大区域; 从所述第一伪图案中去除所述放大区域中的所述第一虚设图案的部分，以产生第一反向虚拟图案; 以及将主图案中的第一图案与第一反向虚拟图案组合以产生用于第一类型特征的第一掩模图案。
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公开(公告)号：US09000798B2
公开(公告)日：2015-04-07
申请号：US13495421
申请日：2012-06-13
Applicant: Jui-Long Chen , Chien-Chih Liao , Tseng Chin Lo , Hui-Yun Chao , Ta-Yung Lee , Jong-I Mou , Chin-Hsiang Lin
Inventor： Jui-Long Chen , Chien-Chih Liao , Tseng Chin Lo , Hui-Yun Chao , Ta-Yung Lee , Jong-I Mou , Chin-Hsiang Lin
IPC: G01R31/02 , G01R31/28 , H01L23/544
CPC classification number: G01R1/07364 , G01R1/06705 , G01R31/2887 , G01R31/2891 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/00 , H01L2924/0002
Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
Abstract translation: 公开了一种用于将诸如晶片级测试探针的探针与晶片接触件对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。
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公开(公告)号：US20130335109A1
公开(公告)日：2013-12-19
申请号：US13495421
申请日：2012-06-13
Applicant: Jui-Long Chen , Chien-Chih Liao , Tseng Chin Lo , Hui-Yun Chao , Ta-Yung Lee , Jong-I Mou , Chin-Hsiang Lin
Inventor： Jui-Long Chen , Chien-Chih Liao , Tseng Chin Lo , Hui-Yun Chao , Ta-Yung Lee , Jong-I Mou , Chin-Hsiang Lin
CPC classification number: G01R1/07364 , G01R1/06705 , G01R31/2887 , G01R31/2891 , H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/5446 , H01L2924/00 , H01L2924/0002
Abstract: A system and method for aligning a probe, such as a wafer-level test probe, with wafer contacts is disclosed. An exemplary method includes receiving a wafer containing a plurality of alignment contacts and a probe card containing a plurality of probe points at a wafer test system. A historical offset correction is received. Based on the historical offset correct, an orientation value for the probe card relative to the wafer is determined. The probe card is aligned to the wafer using the orientation value in an attempt to bring a first probe point into contact with a first alignment contact. The connectivity of the first probe point and the first alignment contact is evaluated. An electrical test of the wafer is performed utilizing the aligned probe card, and the historical offset correction is updated based on the orientation value.
Abstract translation: 公开了一种用于将诸如晶片级测试探针之类的探针与晶片接点对准的系统和方法。 一种示例性方法包括在晶片测试系统处接收包含多个对准触点的晶片和包含多个探针点的探针卡。 接收到历史偏移校正。 基于历史偏移校正，确定探针卡相对于晶片的取向值。 使用取向值将探针卡与晶片对准，以试图使第一探针点与第一对准触点接触。 评估第一探针点和第一对准接触点的连接性。 使用对准的探针卡进行晶片的电气测试，并且基于取向值更新历史偏移校正。
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Patent Agency Ranking
公开(公告)号：US07934173B2
公开(公告)日：2011-04-26
申请号：US12013999
申请日：2008-01-14
Applicant: Jiing-Shin Shyu , Tseng Chin Lo
Inventor： Jiing-Shin Shyu , Tseng Chin Lo
CPC classification number: G03F1/36 , G03F1/80 , H01L27/0203
Abstract: A method of inserting dummy patterns includes providing a window area comprising a main pattern. The main pattern includes first patterns of a first type of features, and second patterns of a second type of features. The first and the second types are different types. The method further includes globally inserting first dummy patterns throughout the window area, wherein the first dummy patterns are dummy patterns of the first type of features; enlarging the main pattern to generate an enlarged main pattern, wherein the enlarged main pattern occupies an enlarged region of the window area; removing the portion of the first dummy patterns in the enlarged region from the first dummy patterns to generate first inversed dummy patterns; and combining the first patterns in the main pattern with the first inversed dummy patterns to generate first mask patterns for the first type of features.
Abstract translation: 插入虚拟图案的方法包括提供包括主图案的窗口区域。 主图案包括第一类型特征的第一图案和第二类型特征的第二图案。 第一类和第二类是不同类型。 该方法还包括在整个窗口区域全局地插入第一虚拟图案，其中第一伪图案是第一类型特征的虚拟图案; 扩大主图案以产生放大的主图案，其中放大的主图案占据窗口区域的扩大区域; 从所述第一伪图案中去除所述放大区域中的所述第一虚设图案的部分，以产生第一反向虚拟图案; 以及将主图案中的第一图案与第一反向虚拟图案组合以产生用于第一类型特征的第一掩模图案。
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公开(公告)号：US07825678B2
公开(公告)日：2010-11-02
申请号：US12196531
申请日：2008-08-22
Applicant: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
Inventor： Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
IPC: G01R31/02
CPC classification number: H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
Abstract translation: 集成电路结构包括半导体晶片; 半导体晶片中的集成电路器件; 以及在半导体晶片的顶表面上并连接到集成电路器件的多个测试焊盘。 测试垫成对分组，同一对中的测试垫互连。
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公开(公告)号：US20080244475A1
公开(公告)日：2008-10-02
申请号：US11731036
申请日：2007-03-30
Applicant: Tseng Chin Lo , Kuo Tsai Li , Shien-Yang Wu
Inventor： Tseng Chin Lo , Kuo Tsai Li , Shien-Yang Wu
IPC: G06F17/50
CPC classification number: G06F17/505 , G06F2217/14
Abstract: A network based integrated circuit testline generating system and method of using the same is described. The system includes a user interface for generating and submitting requests which specify types and configurations of needed testlines for device parametric test. A testline generator receives the requests and creates a layout data base which includes layout information of needed testlines.
Abstract translation: 描述了基于网络的集成电路测试线生成系统及其使用方法。 该系统包括用于生成和提交请求的用户界面，该请求指定用于设备参数测试的所需测试线的类型和配置。 测试线生成器接收请求并创建一个布局数据库，其中包含所需测试线的布局信息。
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公开(公告)号：US06323097B1
公开(公告)日：2001-11-27
申请号：US09590183
申请日：2000-06-09
Applicant: Shien-Yang Wu , Tseng Chin Lo , Konrad Young
Inventor： Shien-Yang Wu , Tseng Chin Lo , Konrad Young
IPC: H01L2120
Abstract: A method and structure is disclosed to measure spacing and misalignment of features in semiconductor integrated circuits. Three equally spaced, parallel first level conductive lines are formed on a first insulating layer with staircase patterns projecting both out of and into the inner edges of the outer lines. A second insulating layer is deposited and step contact vias are opened through the second insulating layer over the steps of the staircase patterns. The inner edge of the step contact via coincides with the inner edge of the step. Contact pad vias are opened through the second insulating layer over the outer lines and the step contact vias and the contact pad vias are filled with conductive material. A second level conductive line is formed over the second insulating layer parallel to said first level conductive lines and above the central first level conductive line. Resistor ladder patterns are formed projecting from both edges of said second level conductive line, the rungs of said ladder patterns being of equal length and being composed of rung conductive sections with a resistor section interposed. A center conductor contact pad is formed electrically connected to the second level conductive line. A right conductor contact pad is formed over the right contact pad via and a left conductor contact pad is formed over the left contact pad via. The resistances between the center conductor pad and the right conductor pad and between the center conductor pad and left conductor pad are measured. From these resistances are inferred which rungs of the resistor ladder patterns make contact with step contact vias of the outer first level conductive lines. This infers bounds for the distances, SR and SL, from the right and left outer first level conductive lines to the second level conductive line. Spacing and misalignment are calculated from these distances.
Abstract translation: 公开了一种用于测量半导体集成电路中的特征的间隔和未对准的方法和结构。 在第一绝缘层上形成三个等间隔的平行的第一级导电线，该第一绝缘层具有从外线的内边缘突出并进入外线的内边缘的阶梯图案。 沉积第二绝缘层，并且在台阶图案的台阶上通过第二绝缘层打开阶梯接触通孔。 台阶接触孔的内边缘与台阶的内边缘重合。 接触焊盘通孔在外线上通过第二绝缘层打开，并且步骤接触通孔和接触焊盘通孔填充有导电材料。 第二级导电线形成在平行于所述第一级导电线并且在中心第一级导电线上方的第二绝缘层上。 电阻梯形图案从所述第二电平导线的两个边缘突出形成，所述梯形图案的梯级具有相等的长度，并且由插入有电阻器部分的梯形导电部分组成。 形成电连接到第二电平导线的中心导体接触焊盘。 在右接触焊盘上形成右导体接触焊盘，并且在左接触焊盘通孔上形成左导体接触焊盘。 测量中心导体焊盘和右导体焊盘之间以及中心导体焊盘和左导体焊盘之间的电阻。 从这些电阻推断出电阻梯形图案的哪个梯级与外部第一级导电线的阶跃接触通孔接触。 这推断了从左右外一级导线到第二级导线的距离SR和SL。 从这些距离计算间距和不对中。
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公开(公告)号：US20100045325A1
公开(公告)日：2010-02-25
申请号：US12196531
申请日：2008-08-22
Applicant: Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
Inventor： Yih-Yuh Doong , Tseng Chin Lo , Chien-Chang Lee , Chih-Chieh Shao
CPC classification number: H01L22/34 , H01L2924/0002 , H01L2924/00
Abstract: An integrated circuit structure includes a semiconductor wafer; integrated circuit devices in the semiconductor wafer; and a plurality of test pads on a top surface of the semiconductor wafer and connected to the integrated circuit devices. Test pads are grouped in pairs, with the test pads in a same pair are interconnected.
Abstract translation: 集成电路结构包括半导体晶片; 半导体晶片中的集成电路器件; 以及在半导体晶片的顶表面上并连接到集成电路器件的多个测试焊盘。 测试垫成对分组，同一对中的测试垫互连。
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