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1.发明申请公开(公告)号：US20120243877A1
公开(公告)日：2012-09-27
申请号：US13425625
申请日：2012-03-21
申请人： Tsugio TAKAHASHI
发明人： Tsugio TAKAHASHI
摘要： An optical receiving apparatus with frame synchronization technology which makes it easy to activate a frame synchronization established state even if bit errors are produced over a transmission link. The apparatus includes: an optoelectrical converting circuit; a pre-stage synchronizing word detecting circuit; a decoder; a post-stage frame synchronization detecting circuit; and a receiver frame synchronization display output circuit.
摘要翻译： 具有帧同步技术的光接收装置，即使在传输链路上产生位错误，也容易激活帧同步建立状态。 该装置包括：光电转换电路; 一个前级同步字检测电路; 解码器 后级帧同步检测电路; 和接收机帧同步显示输出电路。
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2.发明申请公开(公告)号：US20080025346A1
公开(公告)日：2008-01-31
申请号：US11882002
申请日：2007-07-30
申请人： Tsugio Takahashi , Koichi Usami
发明人： Tsugio Takahashi , Koichi Usami
IPC分类号： H04J3/06
CPC分类号： H04J3/0623 , H04J3/0685 , H04J3/1611
摘要： A method and an apparatus for synchronizing and multiplexing asynchronous signals are presented that enable the plurality of asynchronous signals to be processed without increasing the scale of circuitry. Clock phase absorption sections allow respective asynchronous STM-N signals to switch to a system clock signal. In accordance with the system clock signal, a MSOH termination section, a pointer reception section and a memory section carry out MSOH termination processing, frame phase absorption processing and the like in serial on the asynchronous STM-N signals. Synchronous signals thus generated after frame phase absorption are multiplexed through processing of changing pointer values and the like by a pointer transmission section.
摘要翻译： 提出了一种用于同步和复用异步信号的方法和装置，其能够在不增加电路规模的情况下处理多个异步信号。 时钟相位吸收部分允许相应的异步STM-N信号切换到系统时钟信号。 根据系统时钟信号，MSOH终端部分，指针接收部分和存储部分在异步STM-N信号上串行执行MSOH终止处理，帧相位吸收处理等。 在帧相位吸收之后产生的同步信号通过指针传输部分改变指针值等进行复用。
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公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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公开(公告)号：US06538912B2
公开(公告)日：2003-03-25
申请号：US10139330
申请日：2002-05-07
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
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公开(公告)号：US06400596B2
公开(公告)日：2002-06-04
申请号：US09725107
申请日：2000-11-29
申请人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
发明人： Riichiro Takemura , Tomonori Sekiguchi , Katsutaka Kimura , Kazuhiko Kajigaya , Tsugio Takahashi
IPC分类号： G11C1100
CPC分类号： H01L27/10894 , G11C11/4097 , H01L27/10897
摘要： When a phase shift method is used as lithography where sense amplifiers are alternately placed in a one intersecting-point memory capable of implementing a reduction in the area of a DRAM, it was difficult to layout data lines in a boundary region between sense amplifiers and each memory array. Therefore, there is provided a semiconductor device according to the present invention. In the semiconductor device, two data lines continuous within the sub memory arrays or interposed therebetween are connected to the adjacent sense amplifiers as a system for drawing data lines from sub memory arrays (SMA) to sense amplifiers (SA) when the sense amplifiers are alternately placed. Namely, the number of data lines interposed between data lines respectively connected to two adjacent sense amplifiers is set to even numbers (0, 2, 4, . . . ). Owing to the above configuration, a break and a short circuit in a portion where a sense amplifier block and a sub memory array are connected, can be avoided, and a connection layout is facilitated.
摘要翻译： 当使用相移方法作为光刻技术时，将读出放大器交替放置在能够实现DRAM面积减小的一个交叉点存储器中，难以在读出放大器与每个读出放大器之间的边界区域中布置数据线 内存阵列 因此，提供了根据本发明的半导体器件。 在半导体器件中，在副存储器阵列内或插入其间的两条数据线被连接到相邻的读出放大器，作为用于当读出放大器交替地从子存储器阵列（SMA）到读出放大器（SA）的数据线绘制的系统 放置 即，分别连接到两个相邻读出放大器的数据线之间的数据线的数目被设置为偶数（0,2,4 ...）。 由于上述结构，可以避免在读出放大器块和子存储器阵列连接的部分中的断路和短路，并且便于连接布局。
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公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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公开(公告)号：US5499202A
公开(公告)日：1996-03-12
申请号：US253057
申请日：1994-06-02
CPC分类号： G06F7/727
摘要： A residue circuit takes weights of even number bits of a dividend as 1 and weights of odd number bits of the dividend as 2. The circuit includes a plurality of adders for summing bits having weight 1 to output weight 1 at a summing output and weight 2 at a carry output, and a plurality of adders for summing bits having weight 2 to output weight 2 at a summing output and weight 1 at a carry output. With these adders, summing of respective bits of the dividend bits are performed taking the weights into account to repeat summing until the number of bits finally becomes 3 bits. Depending upon the pattern of this 3 bits, a remainder is output by a modulus 3 generation circuit.
摘要翻译： 残余电路将除数的偶数位的权重设为1，并且将被除数的奇数位的权重作为2.该电路包括多个加法器，用于将加权1的位相加以在加法输出和权重2处输出权重1 以及多个加法器，用于对具有权重2的位进行求和，以在加法输出处输出权重2，并在进位输出处加权1。 利用这些加法器，对于重复求和，考虑权重来执行除数比特的各个比特的相加，直到比特数最终变为3比特。 根据该3位的模式，余数由模数3生成电路输出。
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公开(公告)号：US5023648A
公开(公告)日：1991-06-11
申请号：US331304
申请日：1989-03-31
申请人： Hiroshi Meguro , Tsugio Takahashi , Hitoshi Aoki , Toru Kosaka
发明人： Hiroshi Meguro , Tsugio Takahashi , Hitoshi Aoki , Toru Kosaka
摘要： A lens shutter camera comprises a mode signal output device for outputting either a first flash mode signal or a second flash mode signal, a shutter driving device for effecting the opening movement of the lens shutter slowly and effecting the closing movement of the lens shutter quickly when the first flash mode signal is being outputted, and for effecting both of the opening and closing movements of the lens shutter slowly when the second flash mode signal is being outputted, and a flash start signal output device for outputting a flash start signal during the opening movement of the lens shutter when the first flash mode signal is being outputted, and for outputting the flash start signal during the closing movement of the lens shutter when the second flash mode signal is being outputted.
摘要翻译： 镜头快门摄像机包括用于输出第一闪光模式信号或第二闪光模式信号的模式信号输出装置，用于缓慢地进行透镜快门的打开运动并快速实现透镜快门的关闭运动的快门驱动装置， 正在输出第一闪光模式信号，并且用于当输出第二闪光模式信号时缓慢地实现透镜快门的打开和关闭运动;以及闪光启动信号输出装置，用于在打开期间输出闪光启动信号 当输出第一闪光模式信号时透镜快门的移动，并且当输出第二闪光模式信号时在透镜快门的关闭运动期间输出闪光开始信号。
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公开(公告)号：US08943389B2
公开(公告)日：2015-01-27
申请号：US13599490
申请日：2012-08-30
申请人： Tsugio Takahashi
发明人： Tsugio Takahashi
CPC分类号： H03M13/05 , H03M13/19 , H03M13/2703
摘要： A data buffer section stores input words, and outputs them to a first signal line group in order. An error checking and correcting code is generated that has the same number of bits as the words. Some bits are not to be output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups. A code transmission section outputs the error checking and correcting code to different signal lines of the second signal line group respectively, such that a plurality of bits in a code word are not output at the same time within the range of the first and second signal line groups or within the range of a partial signal line group included in the first and second signal line groups.
摘要翻译： 数据缓冲器部分存储输入字，并且按顺序将它们输出到第一信号线组。 生成与字相同位数的错误检查和校正码。 在第一和第二信号线组的范围内或在包括在第一和第二信号线组中的部分信号线组的范围内，一部分位不能同时输出。 代码发送部分分别将错误校验和校正代码输出到第二信号线组的不同信号线，使得码字中的多个比特在第一和第二信号线的范围内不被同时输出 组或包括在第一和第二信号线组中的部分信号线组的范围内。
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10.发明申请PLI N-BIT CORRECTION CIRCUIT, GFP LAYER 2 SYNCHRONIZATION CIRCUIT AND GFP FRAME TRANSFER DEVICE USING IT 审中-公开PLI N-BIT校正电路，GFP层2同步电路和GFP帧传输器件公开(公告)号：US20120011417A1
公开(公告)日：2012-01-12
申请号：US13138644
申请日：2010-03-18
申请人： Tsugio Takahashi
发明人： Tsugio Takahashi
CPC分类号： H04L1/0072 , H04L1/0091 , H04L1/20
摘要： A PLI n-bit correction circuit extracts a core header (PLI) from a GFP frame with a fixed payload length; compares it with a predetermined expectation value for each bit; calculates the number of inconsistent bits therebetween; and outputs the predetermined expectation value, instead of the core header, when the number of inconsistent bits is equal to or less than n (n is a natural number); or directly outputs the core header when the number of inconsistent bits is greater than n. A decision on establishment of GFP Layer 2 synchronization is made based on the output of the PLI n-bit correction circuit, wherein predetermined processing is executed on a payload of a GFP frame dropping its core header when GFP Layer 2 synchronization is established, whilst the payload is not subjected to predetermined processing and discarded in the event of GFP Layer 2 desynchronization.
摘要翻译： PLI n位校正电路从具有固定有效载荷长度的GFP帧中提取核心报头（PLI）; 将其与每个位的预定期望值进行比较; 计算其间不一致位数; 并且当不一致比特的数目等于或小于n（n是自然数）时，输出预定的期望值而不是核心头部; 或者当不一致比特数大于n时，直接输出核心头。 基于PLI n位校正电路的输出进行GFP层2同步的建立决定，其中，当建立GFP层2同步时，对GFP帧丢弃其核心头的有效载荷执行预定处理，而 有效载荷不受预定处理的影响，并在GFP第2层失步的情况下丢弃。
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