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公开(公告)号：US09307651B2
公开(公告)日：2016-04-05
申请号：US13421330
申请日：2012-03-15
申请人： Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Tsung-Yuan Chen , Shu-Sheng Chiang
CPC分类号： H05K3/107 , H05K3/045 , H05K3/423 , H05K3/426 , H05K2201/0376 , H05K2201/09036 , H05K2201/09563 , Y10T29/49155 , Y10T29/49165
摘要： A fabricating process for an embedded circuit structure is provided. A through hole is formed in a core panel and penetrates the core panel. Two indent patterns are respectively formed on two opposite surfaces of the core panel. A conductive material is electroplated into the through hole and the indent patterns, so as to form a conductive channel in the through hole and two circuit patterns in the indent patterns respectively. Portions of the circuit patterns, which exceed the indent patterns respectively, are removed for planarizing the circuit patterns to be level with the two surfaces of the core panel respectively.
摘要翻译： 提供了一种用于嵌入式电路结构的制造工艺。 在芯板中形成贯通孔，贯通芯板。 在芯板的两个相对的表面上分别形成两个压痕图案。 将导电材料电镀到通孔和凹陷图案中，以在通孔中分别形成导电通道和凹陷图案中的两个电路图案。 电路图案的分别超过凹口图案的部分被去除，用于将电路图案平坦化以与芯板的两个表面分级。
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公开(公告)号：US09084379B2
公开(公告)日：2015-07-14
申请号：US13423578
申请日：2012-03-19
申请人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
发明人： Tsung-Yuan Chen , Chun-Chien Chen , Cheng-Po Yu
CPC分类号： H05K3/428 , H05K3/0032 , H05K3/0035 , H05K3/0038 , H05K3/20 , H05K3/205 , H05K2201/09509 , H05K2201/09563 , H05K2201/0969 , H05K2203/0369 , H05K2203/0376 , H05K2203/0384 , H05K2203/0554 , H05K2203/108 , H05K2203/1476 , Y10T29/49124 , Y10T29/49126
摘要： A process for fabricating a wiring board is provided. In the process, a wiring carrying substrate including a carry substrate and a wiring layer is formed. Next, at least one blind via is formed in the wiring carrying substrate. Next, the wiring carrying substrate is laminated to another wiring carrying substrate via an insulation layer. The insulation layer is disposed between the wiring layers of the wiring carrying substrates and full fills the blind via. Next, parts of the carry substrates are removed to expose the insulation layer in the blind via. Next, a conductive pillar connected between the wiring layers is formed. Next, the rest carry substrates are removed.
摘要翻译： 提供一种制造布线板的工艺。 在该过程中，形成包括携带衬底和布线层的布线承载衬底。 接下来，在布线承载基板中形成至少一个盲孔。 接下来，通过绝缘层将布线承载基板层叠到另一布线承载基板。 绝缘层设置在布线基板的布线层之间，并且完全填充盲孔。 接下来，去除部分搬运基板以露出盲孔中的绝缘层。 接下来，形成连接在布线层之间的导电柱。 接下来，其余的携带衬底被去除。
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公开(公告)号：US08365401B2
公开(公告)日：2013-02-05
申请号：US12732512
申请日：2010-03-26
CPC分类号： H05K3/465 , H05K3/0038 , H05K3/06 , H05K2203/0384 , H05K2203/0723 , Y10T29/49155
摘要： A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.
摘要翻译： 电路板包括电路基板，设置在电路基板上的电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有连接到盲孔的第二表面，至少一盲孔，第二凹版图案和第三凹版图案。 图案化电路结构包括至少设置在第二凹版图案中的第二电路和设置在第三凹版图案和盲孔中的第三电路。 每个第三电路具有第一导电层和第二导电层。 第一导电层和第二电路的材料相同。 第二电路的线宽比每个第三电路的线宽短。 至少第三电路电连接到电路基板的第一电路。
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公开(公告)号：US20120312588A1
公开(公告)日：2012-12-13
申请号：US13588882
申请日：2012-08-17
CPC分类号： H05K3/465 , H05K3/0038 , H05K3/06 , H05K2203/0384 , H05K2203/0723 , Y10T29/49155
摘要： A circuit board includes a circuit substrate, a dielectric layer disposed on the circuit substrate and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via, a second intaglio pattern and a third intaglio pattern connected to the blind via. The patterned circuit structure includes at least a second circuit disposed in the second intaglio pattern and third circuits disposed in the third intaglio pattern and the blind via. Each third circuit has a first conductive layer and a second conductive layer. The materials of the first conductive layer and the second circuit are the same. The line width of the second circuit is shorter than that of each third circuit. At least a third circuit is electrically connected to the first circuit of the circuit substrate.
摘要翻译： 电路板包括电路基板，设置在电路基板上的电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有连接到盲孔的第二表面，至少一盲孔，第二凹版图案和第三凹版图案。 图案化电路结构包括至少设置在第二凹版图案中的第二电路和设置在第三凹版图案和盲孔中的第三电路。 每个第三电路具有第一导电层和第二导电层。 第一导电层和第二电路的材料相同。 第二电路的线宽比每个第三电路的线宽短。 至少第三电路电连接到电路基板的第一电路。
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公开(公告)号：US08273651B2
公开(公告)日：2012-09-25
申请号：US12815155
申请日：2010-06-14
IPC分类号： H01L21/4763
摘要： A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method.
摘要翻译： 提供一种制造布线板的布线结构的方法。 首先，提供包括绝缘层和设置在绝缘层上的膜的衬底。 接下来，在膜的外表面上形成露出绝缘层的凹版图案。 通过去除绝缘层的一部分和膜的一部分来形成凹版图案。 接下来，在外表面和凹版图案中形成活化层。 活化层完全覆盖凹版图案的外表面和所有表面。 然后，去除外表面上的膜和活化层，并保留凹版图案中的活化层。 在去除外表面上的膜和活化层之后，通过化学沉积法在凹版图案中形成导电材料。
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公开(公告)号：US20120085569A1
公开(公告)日：2012-04-12
申请号：US13323831
申请日：2011-12-13
申请人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
发明人： Yi-Chun Liu , Wei-Ming Cheng , Tsung-Yuan Chen , Shu-Sheng Chiang
IPC分类号： H05K1/09
CPC分类号： H05K3/465 , H05K3/0032 , H05K3/0035 , H05K3/0055 , H05K3/383 , H05K3/421 , H05K3/4661 , H05K2203/0796 , H05K2203/1383
摘要： An embedded structure of circuit board is provided. The embedded structure includes a substrate, a first patterned conductive layer disposed on the substrate and selectively exposing the substrate, a first dielectric layer covering the first patterned conductive layer and the substrate, a pad opening disposed in the first dielectric layer, and a via disposed in the pad opening and exposing the first patterned conductive layer, wherein the outer surface of the first dielectric layer has a substantially even surface.
摘要翻译： 提供电路板的嵌入式结构。 所述嵌入式结构包括基板，设置在所述基板上并选择性地暴露所述基板的第一图案化导电层，覆盖所述第一图案化导电层和所述基板的第一介电层，设置在所述第一介电层中的焊盘开口， 在所述焊盘开口中并暴露所述第一图案化导电层，其中所述第一介电层的外表面具有基本上均匀的表面。
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7.发明授权Method for simultaneous electronic lapping guide (ELG) and perpendicular magnetic recording (PMR) pole formation 有权同时电子研磨导轨（ELG）和垂直磁记录（PMR）极点形成方法公开(公告)号：US08018678B1
公开(公告)日：2011-09-13
申请号：US12324442
申请日：2008-11-26
申请人： Jinqiu Zhang , Tsung Yuan Chen , Steven C. Rudy
发明人： Jinqiu Zhang , Tsung Yuan Chen , Steven C. Rudy
IPC分类号： G11B5/147
CPC分类号： G11B5/3116 , G11B5/1278 , G11B5/3163 , G11B5/3166 , G11B5/3169
摘要： A method for providing a perpendicular magnetic recording (PMR) head is disclosed. The method comprises: providing a stop layer; providing an insulating layer over the stop layer; forming a pole trench in the insulating layer by performing a reactive ion etching (RIE) process in the insulating layer over the stop layer; forming an electronic lapping guide (ELG) in the insulating layer by performing the RIE process in the insulating layer over the stop layer; and providing a PMR pole in which at least a portion of the PMR pole resides in the pole trench.
摘要翻译： 公开了一种用于提供垂直磁记录（PMR）头的方法。 该方法包括：提供停止层; 在停止层上提供绝缘层; 通过在所述绝缘层上在停止层上进行反应离子蚀刻（RIE）工艺，在所述绝缘层中形成极沟槽; 通过在所述阻挡层上的所述绝缘层中进行RIE处理，在所述绝缘层中形成电子研磨导向器（ELG）; 以及提供PMR极，其中PMR极的至少一部分位于极沟中。
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公开(公告)号：US20110155428A1
公开(公告)日：2011-06-30
申请号：US12785725
申请日：2010-05-24
CPC分类号： H05K3/465 , C23C18/1612 , C23C18/1651 , C23C18/1653 , C23C18/1689 , H05K1/0265 , H05K3/0032 , H05K3/0035 , H05K3/045 , H05K3/107 , H05K2201/0391 , H05K2201/09509 , Y10T29/49155 , Y10T29/49165
摘要： A circuit board includes a circuit substrate, a dielectric layer, and a patterned circuit structure. The dielectric layer covers a first surface and at least a first circuit of the circuit substrate. The dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit, a first intaglio pattern, and a second intaglio pattern. The patterned circuit structure includes at least a second circuit and a plurality of third circuits. The second circuit is disposed in the first intaglio pattern. The third circuits are disposed in the second intaglio pattern and the blind via. Each third circuit has a first conductive layer, a second conductive layer, and a barrier layer. The first conductive layer is located between the barrier layer and the second intaglio pattern and between the barrier layer and the blind via. The second conductive layer covers the barrier layer.
摘要翻译： 电路板包括电路基板，电介质层和图案化电路结构。 电介质层覆盖电路基板的第一表面和至少第一电路。 电介质层具有第二表面，至少从第二表面延伸到第一电路的盲孔，第一凹版图案和第二凹版图案。 图案化电路结构至少包括第二电路和多个第三电路。 第二电路设置在第一凹版图案中。 第三电路设置在第二凹版图案和盲孔中。 每个第三电路具有第一导电层，第二导电层和阻挡层。 第一导电层位于阻挡层和第二凹版图案之间以及阻挡层和盲孔之间。 第二导电层覆盖阻挡层。
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公开(公告)号：US20110147342A1
公开(公告)日：2011-06-23
申请号：US12815155
申请日：2010-06-14
摘要： A method for fabricating a wiring structure of a wiring board is provided. First, a substrate including an insulation layer and a film disposed on the insulation layer is provided. Next, an intaglio pattern exposing the insulation layer is formed on an outer surface of the film. The intaglio pattern is formed by removing a portion of the insulation layer and a portion of the film. Next, an activated layer is formed on the outer surface and in the intaglio pattern. The activated layer completely covers the outer surface and all surfaces of the intaglio pattern. Then, the film and the activated layer on the outer surface are removed, and the activated layer in the intaglio pattern is remained. After the film and the activated layer on the outer surface are removed, a conductive material is formed in the intaglio pattern by chemical deposition method.
摘要翻译： 提供一种制造布线板的布线结构的方法。 首先，提供包括绝缘层和设置在绝缘层上的膜的衬底。 接下来，在膜的外表面上形成露出绝缘层的凹版图案。 通过去除绝缘层的一部分和膜的一部分来形成凹版图案。 接下来，在外表面和凹版图案中形成活化层。 活化层完全覆盖凹版图案的外表面和所有表面。 然后，去除外表面上的膜和活化层，并保留凹版图案中的活化层。 在去除外表面上的膜和活化层之后，通过化学沉积法在凹版图案中形成导电材料。
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公开(公告)号：US20110147056A1
公开(公告)日：2011-06-23
申请号：US12789895
申请日：2010-05-28
CPC分类号： H05K3/465 , H05K3/184 , H05K2201/0347 , H05K2203/1476 , Y10T29/49126 , Y10T29/49155 , Y10T29/49156
摘要： A circuit board including a circuit substrate, a first dielectric layer, an antagonistic activation layer, a first conductive layer, a second conductive layer and a second dielectric layer is provided. The circuit substrate has a first surface and a first circuit layer. The first dielectric layer is disposed on the circuit substrate and covers the first surface and the first circuit layer. The first dielectric layer has a second surface, at least a blind via extending from the second surface to the first circuit layer and an intaglio pattern. The antagonistic activation layer is disposed on the second surface of the dielectric layer. The first conductive layer is disposed in the blind via. The second conductive layer is disposed in the intaglio pattern and the blind via and covers the first conductive layer. The second conductive layer is electrically connected with the first circuit layer via the first conductive layer.
摘要翻译： 提供了包括电路基板，第一介电层，拮抗激活层，第一导电层，第二导电层和第二介电层的电路板。 电路基板具有第一表面和第一电路层。 第一电介质层设置在电路基板上并覆盖第一表面和第一电路层。 第一介电层具有第二表面，至少一个从第二表面延伸到第一电路层的盲孔和凹版图案。 拮抗活化层设置在电介质层的第二表面上。 第一导电层设置在盲孔中。 第二导电层设置在凹版图案和盲孔中并覆盖第一导电层。 第二导电层经由第一导电层与第一电路层电连接。
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