公开(公告)号：US20120242650A1

公开(公告)日：2012-09-27

申请号：US13070490

申请日：2011-03-24

申请人： Yu-Yeh Chen ,  Jia-Jio Huang ,  Jhen-Wei He ,  Heng-Shun Kuan ,  Tsung-Hsien Lin

发明人： Yu-Yeh Chen ,  Jia-Jio Huang ,  Jhen-Wei He ,  Heng-Shun Kuan ,  Tsung-Hsien Lin

IPC分类号： G06T15/00

CPC分类号： H04N13/373 ,  H04N13/122 ,  H04N13/341

摘要： A 3D image processing method, for processing a dynamic image region swapping between a first dynamic image gray level and a second dynamic image gray level, comprising: determining a max dynamic gray level reference value and a min dynamic gray level reference value, to generate an adjusted dynamic gray level and luminance curve; generating a dynamic table, which includes relations between the adjusted dynamic gray level and luminance curve, the first and second dynamic image gray level, according to the adjusted gray level and luminance curve; and adjusting the first and second dynamic image gray level according to the dynamic table.

摘要翻译： 一种3D图像处理方法，用于处理在第一动态图像灰度级和第二动态图像灰度级之间交换的动态图像区域，包括：确定最大动态灰度级参考值和最小动态灰度级参考值，以产生 调整动态灰度级和亮度曲线; 生成动态表，其中包括调整后的动态灰度级和亮度曲线之间的关系，第一和第二动态图像灰度级，根据调整的灰度级和亮度曲线; 并根据动态表调整第一和第二动态图像灰度级。

公开(公告)号：US07916064B2

公开(公告)日：2011-03-29

申请号：US12469749

申请日：2009-05-21

申请人： Tsung-Hsien Lin ,  Chung-Hsing Yang ,  Wei-Hao Chiu

发明人： Tsung-Hsien Lin ,  Chung-Hsing Yang ,  Wei-Hao Chiu

IPC分类号： H03M1/50

CPC分类号： H03M1/50

摘要： A voltage-to-digital converting device includes a first voltage-to-time converter outputting a first delay clock having a first time delay relative to a reference clock in response to an input voltage, and a second voltage-to-time converter outputting a second delay clock having a second time delay relative to the reference clock in response to a feedback voltage. The first and second time delays correspond respectively to the input and feedback voltages. A time-to-digital converting circuit receives the first and second delay clocks from the first and second voltage-to-time converters, compares phases of the first and second delay clocks, generates the feedback voltage based on result of phase comparison made thereby, and outputs a digital signal upon detecting that the phases of the first and second delay clocks are in-phase.

摘要翻译： 电压 - 数字转换装置包括第一电压 - 时间转换器，其响应于输入电压输出相对于参考时钟具有第一时间延迟的第一延迟时钟;以及第二电压 - 时间转换器，其输出 第二延迟时钟响应于反馈电压具有相对于参考时钟的第二时间延迟。 第一和第二时间延迟分别对应于输入和反馈电压。 时间数字转换电路从第一和第二电压 - 时间转换器接收第一和第二延迟时钟，比较第一和第二延迟时钟的相位，基于由此产生的相位比较结果产生反馈电压， 并且在检测到第一和第二延迟时钟的相位是同相的时，输出数字信号。

公开(公告)号：US07851800B2

公开(公告)日：2010-12-14

申请号：US12345666

申请日：2008-12-30

申请人： Tarng-Shiang Hu ,  Yi-Kai Wang ,  Jing-Yi Yan ,  Tsung-Hsien Lin ,  Jia-Chong Ho

发明人： Tarng-Shiang Hu ,  Yi-Kai Wang ,  Jing-Yi Yan ,  Tsung-Hsien Lin ,  Jia-Chong Ho

IPC分类号： H01L31/00

CPC分类号： H01L27/3262 ,  H01L51/524 ,  H01L51/5253 ,  H01L51/5259 ,  H01L2227/323 ,  Y10T428/24802

摘要： A TFT and an OLED device are provided. The TFT includes a substrate, a gate, a gate insulator, a source/drain layer, an isolated layer, and a channel layer. The gate is disposed on the substrate. The gate insulator is disposed on the substrate and covers the gate. The source/drain layer is disposed on the gate insulator, and exposes a portion of the gate insulator above the gate. The isolated layer is disposed on the source/drain layer and has an opening to expose a portion of the gate insulator and a portion of the source/drain layer above the gate. The channel layer is disposed in the opening of the isolated layer. Further, the channel layer is exposed by the opening and is electrically connected to the source/drain layer. On the other hand, the OLED device mainly includes a driving circuit and an organic electro-luminescent unit.

摘要翻译： 提供TFT和OLED装置。 TFT包括衬底，栅极，栅极绝缘体，源极/漏极层，隔离层和沟道层。 栅极设置在基板上。 栅极绝缘体设置在基板上并覆盖栅极。 源极/漏极层设置在栅极绝缘体上，并且将栅极绝缘体的一部分暴露在栅极上方。 隔离层设置在源极/漏极层上并且具有用于暴露栅极绝缘体的一部分和栅极上方的源极/漏极层的一部分的开口。 沟道层设置在隔离层的开口中。 此外，沟道层由开口露出并且电连接到源极/漏极层。 另一方面，OLED器件主要包括驱动电路和有机电致发光单元。

公开(公告)号：US20090298241A1

公开(公告)日：2009-12-03

申请号：US12536492

申请日：2009-08-06

申请人： Yi-Kai Wang ,  Tsung-Hsien Lin ,  Tarng-Shiang Hu ,  Yu-Yuan Shen

发明人： Yi-Kai Wang ,  Tsung-Hsien Lin ,  Tarng-Shiang Hu ,  Yu-Yuan Shen

IPC分类号： H01L21/336

CPC分类号： H01L51/057 ,  Y10S438/944 ,  Y10S438/951

摘要： A method of fabricating a vertical thin film transistor (vertical TFT) is disclosed, wherein a shadow mask is used to fabricate the TFT device in vertical structure. First, a metal layer is formed, which serves as ribs and a gate layer. Next, a shadow mask is disposed on the gate layer. Afterwards, the shadow mask is used as a mask to form a source layer, an organic semiconductor layer and a drain layer. Thus, the process is simplified. Since no photolithography process is required, and therefore damage of the organic semiconductor layer is avoided and a vertical TFT with desired electrical characteristics may be obtained.

摘要翻译： 公开了制造垂直薄膜晶体管（垂直TFT）的方法，其中使用荫罩来制造垂直结构的TFT器件。 首先，形成用作肋和栅极层的金属层。 接下来，在栅极层上设置荫罩。 之后，将荫罩用作掩模以形成源极层，有机半导体层和漏极层。 因此，该过程被简化。 由于不需要光刻工艺，因此避免了有机半导体层的损坏，并且可以获得具有所需电特性的垂直TFT。

公开(公告)号：US20090091484A1

公开(公告)日：2009-04-09

申请号：US11867034

申请日：2007-10-04

申请人： Chan-Hsiang Weng ,  Tsung-Hsien Lin

发明人： Chan-Hsiang Weng ,  Tsung-Hsien Lin

IPC分类号： H03M3/02

CPC分类号： H03M3/37 ,  H03M1/765 ,  H03M3/424 ,  H03M3/438

摘要： The invention provides a continuous-time delta sigma modulator. In one embodiment, the continuous-time delta sigma modulator comprises a series of integrators, a quantizer, and a loop delay compensation circuit. The integrators are coupled in series and generate an analog output signal according to an analog input signal. The quantizer quantizes the analog output signal according to a reference voltage to generate a digital output signal as the output of the continuous-time delta sigma modulator. The loop delay compensation circuit adjusts the reference voltage of the quantizer according to the digital output signal to compensate the continuous-time delta sigma modulator for a loop delay.

摘要翻译： 本发明提供一种连续时间ΔΣ调制器。 在一个实施例中，连续时间ΔΣ调制器包括一系列积分器，量化器和环路延迟补偿电路。 积分器串联耦合，并根据模拟输入信号产生模拟输出信号。 量化器根据参考电压量化模拟输出信号，以产生数字输出信号作为连续时间ΔΣ调制器的输出。 环路延迟补偿电路根据数字输出信号调整量化器的参考电压，以补偿连续时间ΔΣ调制器的环路延迟。

公开(公告)号：US20090061560A1

公开(公告)日：2009-03-05

申请号：US12270863

申请日：2008-11-14

申请人： Tsung-Hsien Lin ,  Jia-Chong Ho ,  Tarng-Shiang Hu ,  Cheng-Chung Lee

发明人： Tsung-Hsien Lin ,  Jia-Chong Ho ,  Tarng-Shiang Hu ,  Cheng-Chung Lee

IPC分类号： H01L21/50

CPC分类号： H01L51/5253 ,  H01L51/525 ,  H01L2251/5338

摘要： A fabricating method of organic electronic device is provided. The method comprises: providing a flexible substrate; fabricating a plurality of organic elements on the flexible substrate; depositing a spacing material layer on the flexible substrate; patterning the spacing material layer to form a patterned spacing layer; and arranging a cover substrate on the patterned spacing layer, and sealing the edges of the flexible substrate and the cover substrate with a sealant, wherein the patterned spacing layer is used to maintain a space between the flexible substrate and the cover substrate.

摘要翻译： 提供了一种有机电子器件的制造方法。 该方法包括：提供柔性基底; 在柔性基板上制造多个有机元件; 在柔性基板上沉积间隔材料层; 图案化间隔材料层以形成图案化间隔层; 以及在图案化的间隔层上布置盖基板，并用密封剂密封柔性基板和盖基板的边缘，其中图案化的间隔层用于保持柔性基板和盖基板之间的空间。

公开(公告)号：US20080094558A1

公开(公告)日：2008-04-24

申请号：US11974283

申请日：2007-10-12

申请人： Chun-Jui Wang ,  I-Lin Ho ,  Pei-Shan Tu ,  Tsung-Hsien Lin

发明人： Chun-Jui Wang ,  I-Lin Ho ,  Pei-Shan Tu ,  Tsung-Hsien Lin

IPC分类号： G02F1/1337 ,  G02F1/1343

CPC分类号： G02F1/133707 ,  G02F1/134309 ,  G02F2001/134318

摘要： A liquid crystal display device is provided that has a plurality of pixel regions where some of the pixel regions have liquid crystal molecules that operate according to both twisted nematic mode and vertical alignment mode.

摘要翻译： 提供了一种液晶显示装置，其具有多个像素区域，其中一些像素区域具有根据扭曲向列模式和垂直取向模式操作的液晶分子。

公开(公告)号：US07174144B2

公开(公告)日：2007-02-06

申请号：US10243854

申请日：2002-09-13

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H04B1/06

CPC分类号： H03L7/0891

摘要： Calibration of a phase locked loop and applications thereof within a radio frequency integrated circuit begins by determining an intersection of an up current and down current produced by a charge pump within the phase locked loop. The RFIC then determines a reference voltage corresponding to the intersection, which varies from an ideal voltage of VDD/2 based on process variations. The RFIC then offsets a control voltage to the voltage control oscillator (VCO) of the phase locked loop based on the reference voltage. Accordingly, by determining the offset of the actual intersection from the ideal intersection, the control voltage to the VCO may be adjusted thereby calibrating the phase locked loop for more linear performance.

摘要翻译： 锁相环的校准及其在射频集成电路中的应用通过确定锁相环内的电荷泵产生的上升电流和下降电流的交点开始。 然后，RFIC确定对应于交点的参考电压，其基于过程变化从VLS2 / 2的理想电压变化。 然后，RFIC基于参考电压将控制电压偏移到锁相环的压控振荡器（VCO）。 因此，通过确定实际交叉点与理想交点的偏移，可以调节到VCO的控制电压，从而校准锁相环以获得更多的线性性能。

公开(公告)号：US06975840B2

公开(公告)日：2005-12-13

申请号：US10159365

申请日：2002-05-31

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H04B1/40

CPC分类号： H04B1/406

摘要： A radio transceiver includes a charge pump formed within a local oscillator that adjusts a voltage input to a voltage-controlled oscillator in a manner that flattens a response curve for small changes in voltage due to a variety of effects including channel length modulation. Thus, a local oscillation tends to provide a greater degree of stability. More specifically, the charge pump of the transceiver includes a pair of feedback circuits that source an additional amount of current into a filter to slightly increase a voltage input to the voltage-controlled oscillator in response to small upward changes in output voltage levels (input with respect to the voltage-controlled oscillator). Similarly, when the output voltage level drops slightly, a second feedback circuit causes a small amount of current to be sinked from the output node thereby slightly decreasing the input voltage to the voltage-controlled oscillator. Thus, the inventive charge pump produces better matching between IUP and IDOWN thus operating to produce a response curve that tends to be flatter in response to small voltage changes due to circuit conditions.

摘要翻译： 无线电收发器包括形成在本地振荡器内的电荷泵，其以由于包括沟道长度调制的各种效应使电压的小变化变平的方式调节对压控振荡器的电压输入。 因此，局部振荡倾向于提供更大程度的稳定性。 更具体地，收发器的电荷泵包括一对反馈电路，其将额外的电流量输入到滤波器中，以便响应于输出电压电平的小的向上变化（输入与 相对于压控振荡器）。 类似地，当输出电压电平略微下降时，第二反馈电路使得少量电流从输出节点吸收，从而略微降低到压控振荡器的输入电压。 因此，本发明的电荷泵在I UP 和I DOWN 之间产生更好的匹配，从而产生响应于由于电路的小电压变化而变得更平坦的响应曲线 条件。

公开(公告)号：US06693476B1

公开(公告)日：2004-02-17

申请号：US10201152

申请日：2002-07-23

申请人： Tsung-Hsien Lin

发明人： Tsung-Hsien Lin

IPC分类号： H03K3289

CPC分类号： H03K3/356139 ,  H03K3/0375 ,  H03K23/667

摘要： A differential latch includes a sample transistor section, a hold transistor section, a 1st gating circuit and a 2nd gating circuit. The sample transistor section is operably coupled to sample, when coupled to a supply voltage (e.g., VDD and VSS) a differential input signal. The hold transistor section is operably coupled to latch, when coupled to the supply voltage, the sampled differential input to produce a latched differential signal. The 1st gating circuit is operable to couple the sampled transistor section to the supply voltage in accordance with a 1st clocking logic operation and a 2nd clocking logic operation. The 2nd gating circuit is operable to couple the hold transistor section to the supply voltage in accordance with a 3rd clocking logic operation and a 4th clocking logic operation.

摘要翻译： 差分锁存器包括采样晶体管部分，保持晶体管部分，第1门控电路和第2门控电路。 当与电源电压（例如，VDD和VSS）耦合到差分输入信号时，采样晶体管部分可操作地耦合到采样。 当耦合到电源电压时，保持晶体管部分可操作地耦合到锁存器，以产生锁存的差分信号。 第一门控电路可操作以根据时钟逻辑运算和第二时钟逻辑运算将采样的晶体管部分耦合到电源电压。 第二门控电路可操作以根据3时钟逻辑运算和4时钟逻辑运算将保持晶体管部分耦合到电源电压。