公开(公告)号：US20120176150A1

公开(公告)日：2012-07-12

申请号：US12987969

申请日：2011-01-10

Applicant: Hsing-Chou Hsu ,  Sheng-Fan Yang ,  Wei-Da Guo ,  Jui-Ni Lee ,  Tung-Yang Chen

Inventor： Hsing-Chou Hsu ,  Sheng-Fan Yang ,  Wei-Da Guo ,  Jui-Ni Lee ,  Tung-Yang Chen

IPC: G01R31/20

CPC classification number: G01R27/32

Abstract: A measuring equipment, such as a vector network analyzer, is provided. The measuring equipment includes a first port and a second port, a probe connected to the first port, an antenna connected to the second port, and a test board corresponding to a type of a device-under-test. A probe-effect is obtained by measuring the test board via the probe and the antenna.

Abstract translation: 提供了测量设备，如矢量网络分析仪。 测量设备包括第一端口和第二端口，连接到第一端口的探头，连接到第二端口的天线以及对应于被测器件类型的测试板。 通过探头和天线测量测试板可获得探针效应。

公开(公告)号：US08196078B2

公开(公告)日：2012-06-05

申请号：US12703770

申请日：2010-02-11

Applicant: Tung-Yang Chen ,  Ching-Ling Tsai ,  Sheng-Fan Yang ,  Jui-Ni Lee

Inventor： Tung-Yang Chen ,  Ching-Ling Tsai ,  Sheng-Fan Yang ,  Jui-Ni Lee

IPC: G06F17/50 ,  G06F11/22

CPC classification number: G01R31/002

Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

Abstract translation: 一种用于预测和调试集成电路（IC）系统的电磁干扰（EMI）特性的方法包括以下步骤：根据IC系统的转换的原始数据选择频域范围以产生阻塞频率分析结果，其中转换的 原始数据通过时间 - 频率波形变换进行变换; 设置标准数据; 将阻塞频率分析结果与准则数据进行比较以产生至少一个比较结果; 以及当处理单元确定通过每个比较结果时，生成通过分析报告; 否则执行EMI设计时频分析。

公开(公告)号：US08120441B2

公开(公告)日：2012-02-21

申请号：US12628221

申请日：2009-12-01

Applicant: Hsing-Chou Hsu ,  Tung-Yang Chen

Inventor： Hsing-Chou Hsu ,  Tung-Yang Chen

IPC: H01P3/08

CPC classification number: H05K1/0224 ,  H05K2201/09236

Abstract: A circuit board includes a signal line plane and a reference plane. The signal line plane has at least a first transmission line and a second transmission line formed thereon. The reference plane has a conductive region and at least a non-conductive region. The first transmission line and the second transmission line overlap the conductive region in a thickness direction of the circuit board. The non-conductive region includes at least a first part and a second part connected to the first part, where the second part is positioned between the projection of the first transmission line on the reference plane and the projection of the second transmission line on the reference plane, and has no intersection with at least one of the projection of the first transmission line and the projection of the second transmission line.

Abstract translation: 电路板包括信号线平面和参考平面。 信号线平面具有形成在其上的至少第一传输线和第二传输线。 参考平面具有导电区域和至少一个非导电区域。 第一传输线和第二传输线在电路板的厚度方向与导电区重叠。 非导电区域包括至少第一部分和连接到第一部分的第二部分，其中第二部分位于参考平面上的第一传输线的投影和第二传输线在参考平面上的投影之间 并且与第一传输线的投影和第二传输线的投影中的至少一个没有交叉。

公开(公告)号：US20110156211A1

公开(公告)日：2011-06-30

申请号：US12650468

申请日：2009-12-30

Applicant: Tung-Yang Chen

Inventor： Tung-Yang Chen

IPC: H01L27/06

CPC classification number: H01L27/0259

Abstract: The semiconductor structure of the present invention comprises: a P-well, a first N+ diffusion region, a first P+ diffusion region, a second P+ diffusion region, a first N-well, and a second N+ diffusion region. The semiconductor structure of the present invention comprises: a N-well, a first P+ diffusion region, a first N+ diffusion region, a second N+ diffusion region, a first P-well, and a second P+ diffusion region. Compared with the conventional semiconductor structure for realizing an ESD protection circuit, the semiconductor structure of the present invention requires a smaller area by utilizing the parasitic BJT to have the same ESD protection function. Brief summarized, the semiconductor structure disclosed by the present invention can be utilized for realizing an ESD protection circuit in a smaller area to reduce cost.

Abstract translation: 本发明的半导体结构包括：P阱，第一N +扩散区，第一P +扩散区，第二P +扩散区，第一N阱和第二N +扩散区。 本发明的半导体结构包括：N阱，第一P +扩散区，第一N +扩散区，第二N +扩散区，第一P阱和第二P +扩散区。 与用于实现ESD保护电路的常规半导体结构相比，本发明的半导体结构通过利用寄生BJT具有相同的ESD保护功能需要较小的面积。 综上所述，本发明公开的半导体结构可以用于在较小的区域中实现ESD保护电路，以降低成本。

公开(公告)号：US20100235798A1

公开(公告)日：2010-09-16

申请号：US12703770

申请日：2010-02-11

Applicant: Tung-Yang Chen ,  Ching-Ling Tsai ,  Sheng-Fan Yang ,  Jui-Ni Lee

Inventor： Tung-Yang Chen ,  Ching-Ling Tsai ,  Sheng-Fan Yang ,  Jui-Ni Lee

IPC: G06F17/50

CPC classification number: G01R31/002

Abstract: A method for predicting and debugging electromagnetic interference (EMI) characteristics of an integrated circuit (IC) system includes the following steps: selecting a frequency domain range according to transformed raw data of the IC system to generate a blocking frequency analysis result, wherein the transformed raw data are transformed by a time-frequency waveform transformation; setting criteria data; comparing the blocking frequency analysis result with the criteria data to generate at least one comparison result; and generating a pass analysis report when a processing unit determines that each comparison result is passed; otherwise, executing an EMI design time-frequency analysis.

Abstract translation: 一种用于预测和调试集成电路（IC）系统的电磁干扰（EMI）特性的方法包括以下步骤：根据IC系统的转换的原始数据选择频域范围以产生阻塞频率分析结果，其中转换的 原始数据通过时间 - 频率波形变换进行变换; 设置标准数据; 将阻塞频率分析结果与准则数据进行比较以产生至少一个比较结果; 以及当处理单元确定通过每个比较结果时，生成通过分析报告; 否则执行EMI设计时频分析。

公开(公告)号：US20090267584A1

公开(公告)日：2009-10-29

申请号：US12107902

申请日：2008-04-23

Applicant: Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

Inventor： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

IPC: G05F5/00

CPC classification number: G01R19/0053 ,  G01R31/002

Abstract: A transient detection circuit coupled between a first power line and a second power line and including a first control unit, a setting unit, and a voltage regulation unit. The first control unit generates a first control signal. The first control signal is at a first level when an electrostatic discharge (ESD) event occurs. The first control signal is at a second level when the ESD event does not occur. The setting unit sets a first node. The first node is set at the second level when the first control signal is at the first level. The voltage regulation unit regulates the first node. The voltage regulation unit regulates the level of the first node at the second level when the first control signal is at the second level.

Abstract translation: 耦合在第一电力线和第二电力线之间并包括第一控制单元，设定单元和电压调节单元的瞬态检测电路。 第一控制单元产生第一控制信号。 当静电放电（ESD）事件发生时，第一控制信号处于第一电平。 当ESD事件不发生时，第一控制信号处于第二级。 设置单元设置第一个节点。 当第一控制信号处于第一级时，第一节点被设置在第二级。 电压调节单元调节第一节点。 当第一控制信号处于第二电平时，电压调节单元调节处于第二电平的第一节点的电平。

公开(公告)号：US20090187361A1

公开(公告)日：2009-07-23

申请号：US12018229

申请日：2008-01-23

Applicant: Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

Inventor： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Chi-Sheng Liao ,  Tung-Yang Chen

IPC: G01R19/00 ,  G01R29/12

CPC classification number: G01R31/001

Abstract: A transient detection circuit including a detecting unit, a setting unit, and a memory unit. The transient detection circuit provides an information signal to an external instrument when an electrostatic discharge (ESD) event occurs. The detecting unit is coupled between a first power line and a second power line for detecting the ESD event. The setting unit sets a level of a first node according to the detection result. The memory unit controls the information signal according to the level of the first node. The information signal is at a first level when the ESD event occurs in the first power line.

Abstract translation: 一种瞬态检测电路，包括检测单元，设定单元和存储单元。 当发生静电放电（ESD）事件时，瞬态检测电路向外部仪器提供信息信号。 检测单元耦合在用于检测ESD事件的第一电力线和第二电力线之间。 设置单元根据检测结果设置第一节点的级别。 存储单元根据第一节点的电平来控制信息信号。 当ESD事件发生在第一电力线中时，信息信号处于第一电平。

公开(公告)号：US07023678B2

公开(公告)日：2006-04-04

申请号：US11193773

申请日：2005-07-28

Applicant: Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

Inventor： Ming-Dou Ker ,  Cheng-Ming Lee ,  Tung-Yang Chen

IPC: H02H9/00

CPC classification number: H01L27/0288 ,  H01L23/60 ,  H01L24/06 ,  H01L27/0255 ,  H01L2924/14 ,  H01L2924/3011 ,  H01L2924/00

Abstract: An ESD protection circuit design incorporating a single, or a plurality of, parallel inductor and capacitor, also known as LC tank(s), to avoid power loss by parasitic capacitance in ESD circuits. The first design described incorporates a LC tank structure. The second includes two LC tank structures. These structures can be expanded to form ESD protection circuit structures stacked with n-stages LC tanks. The last design described is ESD protection circuits formed by stacking the first design. These designs can avoid power gain loss from parasitic capacitance of ESD, because the parameters of LC tank can be designed to resonant at a desired operating frequency. Each of these designs can be altered slightly to create variant designs with equal identical ESD protection capabilities.

公开(公告)号：US09001478B2

公开(公告)日：2015-04-07

申请号：US13329033

申请日：2011-12-16

Applicant: Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen ,  Ching-Ling Tsai ,  Shih-Fan Chen

Inventor： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen ,  Ching-Ling Tsai ,  Shih-Fan Chen

IPC: H02H9/00 ,  H03M1/36 ,  G01R19/00

CPC classification number: H03M1/361 ,  G01R19/0053

Abstract: A self-reset transient-to-digital convertor which includes at least one transient detection circuit is disclosed. The transient detection circuit, coupled between a first power line and a second power line, includes at least one voltage drop unit, a current amplifier unit, and a time control unit. When an ESD event occurs, the voltage drop unit is conducted to pass through an ESD current. The current amplifier unit, coupled between the voltage drop unit and the first power line, is conducted by the ESD current to set the level of a first node. The time control unit, coupled between the first node and the second power line, is configured to gradually drain the ESD current away. Wherein, each of the transient detection circuit generates a digital code according to the level of the first node.

Abstract translation: 公开了一种包括至少一个瞬态检测电路的自复位瞬态 - 数字转换器。 耦合在第一电力线和第二电力线之间的瞬态检测电路包括至少一个压降单元，电流放大器单元和时间控制单元。 当ESD事件发生时，电压降单元被传导通过ESD电流。 耦合在电压降单元和第一电力线之间的电流放大器单元由ESD电流进行，以设定第一节点的电平。 耦合在第一节点和第二电力线之间的时间控制单元配置成逐渐将ESD电流消耗掉。 其中，每个瞬态检测电路根据第一节点的电平产生数字码。

公开(公告)号：US08649135B2

公开(公告)日：2014-02-11

申请号：US13050157

申请日：2011-03-17

Applicant: Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen

Inventor： Ming-Dou Ker ,  Cheng-Cheng Yen ,  Tung-Yang Chen

IPC: H02H9/00

CPC classification number: H03K19/00369

Abstract: A noise filter circuit for an IC is provided. The noise filter circuit comprises a decoupling unit coupled to a power pad of the IC and a current amplifier circuit coupled to the decoupling unit and the power pad of the IC. The decoupling unit generates a first current in response to a transient voltage being on the power pad of the IC. The current amplifier circuit drains a second current from the power pad of the IC according to the first current.

Abstract translation: 提供了一种用于IC的噪声滤波器电路。 噪声滤波器电路包括耦合到IC的功率垫的去耦单元和耦合到解耦单元和IC的功率垫的电流放大器电路。 解耦单元响应于在IC的功率垫上的瞬态电压产生第一电流。 当前放大器电路根据第一电流从IC的功率垫排出第二电流。