公开(公告)号：US11227848B2

公开(公告)日：2022-01-18

申请号：US15636644

申请日：2017-06-29

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Wen-Yuan Chang ,  Wei-Cheng Chen ,  Hsueh-Chung Shelton Lu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L21/56 ,  H01L25/04 ,  H01L23/31 ,  H01L27/00

Abstract: A chip package array including a plurality of chip packages is provided. The chip packages are suitable for array arrangement to form the chip package array. Each of the chip packages includes a redistribution structure, a supporting structure, a chip, and an encapsulated material. The supporting structure is disposed on the redistribution structure and has an opening. The chip is disposed on the redistribution structure and located in the opening. The encapsulated material is located between the opening and the chip, wherein the encapsulated material is filled between the opening and the chip, and the chip and the supporting structure are respectively connected to the redistribution structure.

公开(公告)号：US11038697B2

公开(公告)日：2021-06-15

申请号：US15348285

申请日：2016-11-10

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Kai Li ,  Yun Shen ,  Hui Li

IPC: H04L9/32 ,  G06F9/4401 ,  G06F21/44 ,  G06F21/57 ,  H04L9/14 ,  H04L9/30 ,  H04L9/06

Abstract: Apparatuses and methods for trusted module execution are proposed, which provide secure boot and trusted execution of system software by using the China commercial cryptography algorithms to establish the SRTM/DRTM. Conventionally, the Intel TXT which uses RSA or SHA-256 cryptography algorithms only authenticates the trusted modules. By contrast, the present application uses the China commercial cryptography algorithms and is able to authenticate the trusted modules and their digital certificates or certificate chains (which has a higher security level than just authenticating the digital certificates).

公开(公告)号：US10826850B2

公开(公告)日：2020-11-03

申请号：US16297551

申请日：2019-03-08

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Xiaoliang Kang ,  Jiin Lai ,  Weilin Wang ,  Peng Shen

IPC: H04L12/861 ,  H04L29/08 ,  H04L12/935 ,  H04L29/06

Abstract: A data accessing method of a switch for transmitting data packets between a first source node and a first target node and between a second source node and a second target node includes: transmitting a data packet to the switch via at least one of the first communication link and the third communication link and configuring the control unit to store information contained in the data packet into the storage unit; and retrieving the information contained in the data packet from the storage unit via at least one of the second communication link and the fourth communication link. The first source node, the second source node, the first target node and the second target node share the same storage blocks.

公开(公告)号：US10565494B2

公开(公告)日：2020-02-18

申请号：US15396571

申请日：2016-12-31

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： G. Glenn Henry ,  Kim C. Houck ,  Parviz Palangpour

IPC: G06N3/00 ,  G06N3/063 ,  G06F12/0862 ,  G06N3/04 ,  G06F9/38 ,  G06F9/30

Abstract: First/second memories hold rows of N weight/data words. Each of N processing units (PU) of index J have a register, an accumulator having an output, an arithmetic unit that performs an operation thereon to accumulate a result, the first input receives the output of the accumulator, the second input receives a respective first memory weight word, the third input receives a respective data word output by the register, and multiplexing logic receives a respective second memory data word and a data word output by the register of PU J−1 and outputs a selected data word to the register. PU J−1 for PU 0 is PU N−1. The multiplexing logic of PU 0 also receives the data word output by the register of PU (N/2)−1. The multiplexing logic of PU N/2 also receives the data word output by the register of PU N−1.

公开(公告)号：US10564932B2

公开(公告)日：2020-02-18

申请号：US15426391

申请日：2017-02-07

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Zhi Zhang ,  Jing Chen

IPC: G06F7/499 ,  G06F7/483

Abstract: The invention introduces a method for calculating floating-point operands, which contains at least the following steps: receiving an FP (floating-point) operand in a first format from a source register, wherein the first format is one of a group of first formats of different kinds; converting the FP operand in the first format into an FP operand in a second format; generating a calculation result in the second format by calculating the FP operand in the second format; converting the calculation result in the second format into a calculation result in the first format; and writing-back the calculation result of the first format.

公开(公告)号：US10552370B2

公开(公告)日：2020-02-04

申请号：US15090814

申请日：2016-04-05

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： G. Glenn Henry ,  Terry Parks ,  Kyle T. O'Brien

IPC: G06N3/04 ,  G06F15/82 ,  G06F1/10 ,  G06F9/30 ,  G06F9/32 ,  G06F9/38 ,  G06F9/445 ,  G06N3/063 ,  G06N3/08 ,  G06F7/499 ,  G06F7/483

Abstract: A neural network unit has at least one RAM, an output buffer and an array of neural processing units that: read first time step context layer node values from the output buffer; read second time step input layer node values from the RAM; generate second time step hidden layer node values based on the read input and context layer node values; output the hidden layer node values to the output buffer rather than to the RAM; read the hidden layer node values from the output buffer; generate second time step context layer node values based on the read hidden layer node values; output the context layer node values to the output buffer rather than to the RAM; generate output layer node values using the hidden layer node values; write the output layer node values to the RAM; and repeat for a sequence of time steps.

公开(公告)号：US10474628B2

公开(公告)日：2019-11-12

申请号：US15090701

申请日：2016-04-05

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06F9/30 ,  G06N3/063 ,  G06F9/38 ,  G06F15/82 ,  G06F1/10 ,  G06N3/04 ,  G06F9/445 ,  G06N3/08 ,  G06F7/499 ,  G06F7/483 ,  G06F9/32

Abstract: A processor has functional units that fetch and decode architectural instructions of an architectural instruction set at a first rate, a register that stores a value of an indicator programmable by execution of an architectural instruction of the architectural instruction set, and an execution unit. The execution unit includes a first memory that holds data, a second memory that holds instructions of a program, and a plurality of processing units that execute the program instructions at a second rate to perform operations on data received from the first memory to generate results to be written to the first memory. The instructions are of an instruction set that is distinct from the architectural instruction set. The second rate is the first rate when the indicator is programmed with a first value and the second rate is less than the first rate when the indicator is programmed with a second value.

公开(公告)号：US10395165B2

公开(公告)日：2019-08-27

申请号：US15366018

申请日：2016-12-01

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： G. Glenn Henry ,  Kim C. Houck

IPC: G06N3/04 ,  G06N3/063

Abstract: N processing units (PU) each have an arithmetic unit (AU) that performs an operation on first, second and third inputs to generate a result to store in an accumulator having an output provided to the first input. A weight input is received by the AU second input. A multiplexed register has first, second, third and fourth data inputs and an output received by the third AU input. A first memory provides N weight words to the N weight inputs. A second memory provides N data words to the multiplexed register first data inputs. The multiplexed register output is also received by the second, third, and fourth data input of the multiplexed register one, 2{circumflex over ( )}J, and 2{circumflex over ( )}K PUs away, respectively. The N multiplexed registers collectively operate as an N-word rotater that rotates by one, 2{circumflex over ( )}J, or 2{circumflex over ( )}K words when the control input specifies the second, third, or fourth data input, respectively.

公开(公告)号：US10394574B2

公开(公告)日：2019-08-27

申请号：US15171388

申请日：2016-06-02

Applicant: VIA Alliance Semiconductor Co., Ltd.

Inventor： Fengxia Wu ,  Tian Shen ,  Zhou Hong ,  Yuanfeng Wang

IPC: G06F9/38 ,  G06F9/445

Abstract: An apparatus for enqueuing kernels on a device-side is introduced to incorporate with at least a MXU (Memory Access Unit) and a CSP (Command Stream Processor): The CSP, after receiving a first command from the MXU, executes commands of a ring buffer, thereby enabling an EU (Execution Unit) to direct the MXU to allocate space of the ring buffer for a first hardware thread and subsequently write second commands of the first hardware thread into the allocated space of the ring buffer according to an instruction of a kernel.

公开(公告)号：US10380064B2

公开(公告)日：2019-08-13

申请号：US15090696

申请日：2016-04-05

Applicant: VIA ALLIANCE SEMICONDUCTOR CO., LTD.

Inventor： G. Glenn Henry ,  Terry Parks

IPC: G06N3/04 ,  G06N3/063 ,  G06F15/82 ,  G06F1/10 ,  G06F9/30 ,  G06F9/445 ,  G06N3/08 ,  G06F9/38 ,  G06F7/499 ,  G06F7/483 ,  G06F9/32

Abstract: A neural network unit including a register programmable with a representation of a reciprocal value of a divisor and a plurality of neural processing units (NPU). Each NPU has an ALU, an accumulator, and a reciprocal multiplier unit. The ALU performs arithmetic and logical operations on a sequence of operands to generate a sequence of results and accumulates the sequence of results as an accumulated value into the accumulator. The reciprocal multiplier unit receives the representation of the reciprocal value and the accumulated value and in response generates a result that is the quotient of the accumulated value and the divisor.