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公开(公告)号：US20100156457A1
公开(公告)日：2010-06-24
申请号：US12340358
申请日：2008-12-19
IPC分类号： H03K19/177 , H03K19/0175
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。
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公开(公告)号：US07538379B1
公开(公告)日：2009-05-26
申请号：US11303865
申请日：2005-12-16
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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公开(公告)号：US07898018B2
公开(公告)日：2011-03-01
申请号：US12359481
申请日：2009-01-26
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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4.发明申请公开(公告)号：US20100038697A1
公开(公告)日：2010-02-18
申请号：US12370828
申请日：2009-02-13
IPC分类号： H01L27/115 , H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。
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公开(公告)号：US20090159954A1
公开(公告)日：2009-06-25
申请号：US12359481
申请日：2009-01-26
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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6.发明申请公开(公告)号：US20070215935A1
公开(公告)日：2007-09-20
申请号：US11750650
申请日：2007-05-18
IPC分类号： H01L29/788
CPC分类号： H01L27/0203 , H01L21/823493 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11524
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
摘要翻译： 在半导体本体中形成双晶体管非易失性存储单元。 记忆晶体管阱设置在半导体本体内。 开关晶体管阱设置在半导体本体内并与存储晶体管良好地电隔离。 包括间隔开的源极和漏极区域的存储晶体管形成在存储器晶体管阱内。 在开关晶体管阱区内形成包括间隔开的源极和漏极区的开关晶体管。 浮置栅极与存储晶体管和开关晶体管的源极和漏极区域绝缘并自对准。 控制栅极设置在浮置栅极之上并与存储晶体管的源极和漏极区域以及开关晶体管对准。
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公开(公告)号：US07915665B2
公开(公告)日：2011-03-29
申请号：US12417189
申请日：2009-04-02
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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公开(公告)号：US07884640B2
公开(公告)日：2011-02-08
申请号：US12340358
申请日：2008-12-19
IPC分类号： H03K19/173
CPC分类号： H03K19/17784
摘要： A programmable logic device (PLD) with a plurality of programmable regions is disclosed. Some of the programmable regions have switch power or ground supplies to allow them to be put into a low-power state in one or more low-power modes. At least one of the programmable regions always remains on during the low-power modes to enable the user to design custom PLD power management logic that may be placed in the always-on programmable region.
摘要翻译： 公开了具有多个可编程区域的可编程逻辑器件（PLD）。 一些可编程区域具有开关电源或接地电源，以允许它们在一个或多个低功率模式下进入低功率状态。 在低功率模式期间，至少一个可编程区域始终保持接通状态，以使用户能够设计定制的PLD功率管理逻辑，该逻辑可以放置在永久可编程区域中。
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公开(公告)号：US07768317B1
公开(公告)日：2010-08-03
申请号：US12124661
申请日：2008-05-21
IPC分类号： H03K19/094
CPC分类号： H03K19/00392 , G11C5/005 , G11C7/24 , G11C16/0441
摘要： A radiation-tolerant flash-based FPGA switching element includes a plurality of memory cells each having a memory transistor and a switch transistor sharing a floating gate. Four such memory cells are combined such that two sets of two switch transistors are wired in series and the two sets of series-wired switch transistors are also wired in parallel. The four memory transistors associated with the series-parallel combination of switch transistors are all programmed to the same on or off state. The series combination prevents an “on” radiation-hit fault to one of the floating gates from creating a false connection and the parallel combination prevents an “off” radiation-hit fault to one of the floating gates from creating a false open circuit.
摘要翻译： 辐射耐受的基于闪存的FPGA开关元件包括多个存储单元，每个存储单元具有存储晶体管和共享浮置栅极的开关晶体管。 四个这样的存储单元被组合，使得两组开关晶体管串联连接，并且两组串联有线开关晶体管也并联布线。 与开关晶体管的串并联组合相关联的四个存储晶体管都被编程为相同的导通或截止状态。 串联组合防止对其中一个浮动栅极的“导通”辐射命中故障造成假连接，并联并联防止对其中一个浮动栅极的“关闭”辐射命中故障造成假开路。
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公开(公告)号：US07538382B1
公开(公告)日：2009-05-26
申请号：US11927237
申请日：2007-10-29
IPC分类号： H01L29/788
CPC分类号： H01L27/11524 , H01L27/0203 , H01L27/105 , H01L27/115 , H01L27/11519 , H01L27/11521 , H01L27/11526 , H01L27/11529 , H01L29/7881
摘要： A two-transistor non-volatile memory cell is formed in a semiconductor body. A memory-transistor well is disposed within the semiconductor body. A switch-transistor well is disposed within the semiconductor body and is electrically isolated from the memory transistor well. A memory transistor including spaced-apart source and drain regions is formed within the memory-transistor well. A switch transistor including spaced-apart source and drain regions is formed within the switch-transistor well region. A floating gate is insulated from and self aligned with the source and drain regions of the memory transistor and switch transistor. A control gate is disposed above and aligned to the floating gate and with the source and drain regions of the memory transistor and the switch transistor.
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