公开(公告)号：US08772073B2

公开(公告)日：2014-07-08

申请号：US12988110

申请日：2009-04-14

Applicant: Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

Inventor： Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

IPC: H01L21/00 ,  H01L27/146 ,  H01L21/3105

CPC classification number: H01L27/14685 ,  H01L21/31053 ,  H01L21/31111 ,  H01L27/14621 ,  H01L27/14629

Abstract: A method of providing a dielectric material (18) having regions (18′, 18″) with a varying thickness in an IC manufacturing process is disclosed. The method comprises forming a plurality of patterns in respective regions (20′, 20″) of the dielectric material (18), each pattern increasing the susceptibility of the dielectric material (18) to a dielectric material removal step by a predefined amount and exposing the dielectric material (18) to the dielectric material removal step. In an embodiment, the IC comprises a plurality of pixilated elements (12) and a plurality of light interference elements (24), each comprising a first mirror element (16) and a second mirror element (22), a region of the dielectric material (18) separating the first mirror element (16) and the second element (22), and each being arranged over one of said pixilated elements (12), the method further comprising forming the respective first mirror elements (16) in a dielectric layer (14) over a substrate (10) comprising the plurality of pixilated elements; depositing the dielectric material over the dielectric layer; and forming the respective second mirror elements such that each second mirror element is separated from a respective first mirror element by a region of the exposed dielectric material. Hence, an IC having a layer of a dielectric material (18) comprising regions of different thicknesses can be obtained requiring only a few process steps.

Abstract translation: 公开了一种在IC制造过程中提供具有变化厚度的区域（18'，18“）的介电材料（18）的方法。 该方法包括在介电材料（18）的相应区域（20'，20“）中形成多个图案，每个图案将电介质材料（18）的敏感性增加到电介质材料去除步骤预定量并暴露 介电材料（18）到介电材料去除步骤。 在一个实施例中，IC包括多个像素化元件（12）和多个光干涉元件（24），每个元件包括第一镜元件（16）和第二镜元件（22），介电材料的区域 （18）分离第一镜元件（16）和第二元件（22），并且每个被布置在一个所述像素化元件（12）上，所述方法还包括在电介质层中形成相应的第一镜元件（16） （14）包括多个像素化元件的衬底（10）上; 在电介质层上沉积电介质材料; 以及形成各个第二反射镜元件，使得每个第二反射镜元件通过暴露的电介质材料的区域与相应的第一反射镜元件分离。 因此，可以获得具有包括不同厚度的区域的电介质材料层（18）的IC，只需要几个工艺步骤。

公开(公告)号：US08723443B2

公开(公告)日：2014-05-13

申请号：US13257266

申请日：2010-02-25

Applicant: Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

Inventor： Peter Hubertus Franciscus Deurenberg ,  Gert-Jan Koolen ,  Gian Hoogzaad ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  Viet Nguyen Hoang

IPC: H05B33/00

CPC classification number: H05B33/086 ,  H05B33/0815 ,  H05B33/0848

Abstract: A method is disclosed of controlling a LED, comprising driving the LED with a DC current for a first time, interrupting the DC current for a second time such that the first time and the second time sum to a period, determining at least one characteristic of the LED while the DC current is interrupted, and controlling the DC current during a subsequent period in dependence on the at least one characteristic. The invention thus benefits from the simplicity of DC operation. By operating at the LED in a DC mode, rather than say in a PWM mode, the requirement to be able to adjust the duty cycle is avoided. By including interruptions to the DC current, it is possible to utilize the LED itself to act as a sensor in order to determine a characteristic of the LED. The need for additional sensors is thereby avoided.

Abstract translation: 公开了一种控制LED的方法，包括第一次用DC电流驱动LED，第二次中断DC电流，使得第一时间和第二时间总和到一个周期，确定至少一个特性 所述LED在DC电流中断期间，并且根据所述至少一个特性在随后的时段期间控制所述DC电流。 因此，本发明由于DC操作的简单性而受益。 通过在DC模式下操作LED，而不是在PWM模式下说明，可以避免能够调整占空比的要求。 通过包含直流电流的中断，可以利用LED本身作为传感器，以便确定LED的特性。 从而避免了对附加传感器的需要。

公开(公告)号：US08367552B2

公开(公告)日：2013-02-05

申请号：US10526422

申请日：2003-08-04

Applicant: Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

Inventor： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Julma Oscar Maria Hoofman ,  Greja Johanna Adriana Maria Verheijden

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/7684 ,  H01L21/7688

Abstract: The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material on top thereof, depositing a protection layer on top of the dielectric material, depositing a sacrificial layer on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer in the opening and on the sacrificial layer, depositing metal material on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

Abstract translation: 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料的基底，在电介质材料的顶部上沉积保护层，在保护层的顶部上沉积牺牲层，牺牲层的机械强度低于 保护层的机械强度，形成开口）穿过保护层并进入电介质材料，在开口和牺牲层上沉积阻挡层，在阻挡层上沉积金属材料，金属 填充开口的材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层。

公开(公告)号：US08012872B2

公开(公告)日：2011-09-06

申请号：US11718876

申请日：2005-11-02

Applicant: Viet Nguyen Hoang ,  Greja J. A. M. Verheijden

Inventor： Viet Nguyen Hoang ,  Greja J. A. M. Verheijden

IPC: H01L21/4763

CPC classification number: H01L21/76843 ,  H01L21/3212 ,  H01L21/7684 ,  H01L21/76865

Abstract: Manufacturing a damascene structure involves: forming a sacrificial layer (20) on a substrate (10) to protect an area around a recess (30) for the damascene structure, forming a barrier layer (40) in the recess, and in electrical contact with the sacrificial layer, forming the damascene structure (50) in the recess, and planarizing. During the planarizing the sacrificial layer reacts electrochemically with the barrier layer or with the damascene structure. This can alter a relative rate of removal of the damascene structure and the sacrificial layer so as to reduce dishing or protrusion of the damascene structure, and reduce copper residues, and reduce barrier corrosion. The barrier layer can be formed by ALCVD. The barrier material being one or more of WCN and TaN. The sacrificial layer can be TaN, TiN or W.

Abstract translation: 制造镶嵌结构包括：在基底（10）上形成牺牲层（20）以保护用于镶嵌结构的凹部（30）周围的区域，在凹槽中形成阻挡层（40），并与 牺牲层，在凹部中形成镶嵌结构（50）并且平坦化。 在平坦化期间，牺牲层与阻挡层或镶嵌结构电化学反应。 这可以改变镶嵌结构和牺牲层的相对去除速率，以减少镶嵌结构的凹陷或凸起，并且减少铜残留物，并减少屏障腐蚀。 阻挡层可以通过ALCVD形成。 阻挡材料是WCN和TaN中的一种或多种。 牺牲层可以是TaN，TiN或W.

公开(公告)号：US20110150028A1

公开(公告)日：2011-06-23

申请号：US12971738

申请日：2010-12-17

Applicant: Viet NGUYEN HOANG ,  Pascal BANCKEN ,  Radu SURDEANU ,  Benoit BATAILLOU ,  David van STEENWINCKEL

Inventor： Viet NGUYEN HOANG ,  Pascal BANCKEN ,  Radu SURDEANU ,  Benoit BATAILLOU ,  David van STEENWINCKEL

IPC: G01K15/00

CPC classification number: G01K7/01 ,  G01K15/00 ,  H05B33/089

Abstract: The present invention relates to a calibration circuit, computer program product, and method of calibrating a junction temperature measurement of a semiconductor element, wherein respective forward voltages at junctions of the semiconductor element and a reference temperature sensor are measured, and an absolute ambient temperature is determined by using the reference temperature sensor, and the junction temperature of the semiconductor element is predicted based on the absolute ambient temperature and the measured forward voltages.

Abstract translation: 本发明涉及校准电路，计算机程序产品和校准半导体元件的结温测量的方法，其中测量半导体元件和基准温度传感器的接合处的各个正向电压，绝对环境温度为 通过使用参考温度传感器确定，并且基于绝对环境温度和所测量的正向电压来预测半导体元件的结温。

公开(公告)号：US20110097896A1

公开(公告)日：2011-04-28

申请号：US10526422

申请日：2003-08-04

Applicant: Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

Inventor： Roel Daamen ,  Viet Nguyen Hoang ,  Romano Hoofman ,  Greja Verheijoen

IPC: H01L21/768

CPC classification number: H01L21/7684 ,  H01L21/7688

Abstract: The present invention relates to a method for fabrication of in-laid metal interconnects. The method comprises the steps of providing a substrate with a dielectric material (1) on top thereof, depositing a protection layer (2) on top of the dielectric material, depositing a sacrificial layer (7) on top of the protection layer, the sacrificial layer having a mechanical strength that is lower than the mechanical strength of the protection layer, making an opening (3) through the sacrificial layer, through the protection layer and into the dielectric material, depositing a barrier layer (4) in the opening and on the sacrificial layer, depositing metal material (5) on the barrier layer, the metal material filling the opening, removing portions of the metal material existing beyond the opening by means of polishing, and removing the barrier layer and the sacrificial layer in one polishing step.

Abstract translation: 本发明涉及一种内置金属互连的制造方法。 该方法包括以下步骤：在其顶部提供介电材料（1）的基底，在电介质材料的顶部上沉积保护层（2），在保护层的顶部上沉积牺牲层（7） 具有低于保护层的机械强度的机械强度的层，通过保护层形成通过牺牲层的开口（3）并进入电介质材料，在开口中沉积阻挡层（4） 牺牲层，在阻挡层上沉积金属材料（5），填充开口的金属材料，通过抛光去除存在于开口之外的金属材料的部分，以及在一个抛光步骤中去除阻挡层和牺牲层 。

公开(公告)号：US09386655B2

公开(公告)日：2016-07-05

申请号：US12994650

申请日：2009-05-21

Applicant: Viet Nguyen Hoang ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  David Van Steenwinckel

Inventor： Viet Nguyen Hoang ,  Radu Surdeanu ,  Pascal Bancken ,  Benoit Bataillou ,  David Van Steenwinckel

IPC: H01L29/49 ,  H05B33/08 ,  G01J1/02 ,  G01J1/04 ,  G01J1/32 ,  G01J1/42

CPC classification number: H05B33/0869 ,  G01J1/02 ,  G01J1/0209 ,  G01J1/04 ,  G01J1/0407 ,  G01J1/0425 ,  G01J1/32 ,  G01J2001/4247 ,  H05B33/0821

Abstract: A light sensor device comprises a substrate (10) having a well (12) defined in one surface. At least one light sensor (14) is formed at the base of the well (12), and an optical light guide (18) in the form of a transparent tunnel (18) within an opaque body (20) extends from a top surface of the device down a sloped side wall of the well (12) to the location of the light sensor (14).

Abstract translation: 光传感器装置包括具有在一个表面中限定的阱（12）的衬底（10）。 至少一个光传感器（14）形成在井（12）的基部处，并且在不透明体（20）内的透明隧道（18）形式的光导（18）从顶表面 （12）的倾斜的侧壁上的装置到光传感器（14）的位置。

公开(公告)号：US08896317B2

公开(公告)日：2014-11-25

申请号：US12867218

申请日：2009-02-09

Applicant: Radu Surdeanu ,  Viet Nguyen Hoang ,  Benoit Bataillou ,  Pascal Bancken ,  David Van Steenwinckel

Inventor： Radu Surdeanu ,  Viet Nguyen Hoang ,  Benoit Bataillou ,  Pascal Bancken ,  David Van Steenwinckel

IPC: G01R31/02 ,  H05B33/08

CPC classification number: H05B33/0866

Abstract: A method of determining the dominant output wavelength of an LED, includes determining an electrical characteristic of the LED which is dependent on the voltage-capacitance characteristics, and analyzing the characteristic to determine the dominant output wavelength.

Abstract translation: 确定LED的主要输出波长的方法包括确定取决于电压 - 电容特性的LED的电特性，以及分析该特性以确定主要输出波长。

公开(公告)号：US08376801B2

公开(公告)日：2013-02-19

申请号：US12922127

申请日：2009-03-09

Applicant: Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

Inventor： Viet Nguyen Hoang ,  Radu Surdeanu ,  Benoit Bataillou

IPC: H01J9/24

CPC classification number: H05B33/10 ,  Y10T428/24298 ,  Y10T428/24331

Abstract: The present invention relates to a luminescent component (30) and a manufacturing method thereof. The luminescent component (30) comprises a first transparent carrier (18), a second transparent carrier (24), a substrate (10) sandwiched between said transparent carriers (18; 24), the substrate (10) comprising a conduit from the first transparent layer (18) to the second transparent carrier (24), the conduit being filled with a luminescent solution (20). This facilitates the use of colloidal solutions of quantum dots in such a luminescent component (30). Preferably, the substrate (10) is direct bonded to the transparent carriers (18, 24) using direct wafer bonding techniques.

Abstract translation: 本发明涉及发光成分（30）及其制造方法。 发光组件（30）包括第一透明载体（18），第二透明载体（24），夹在所述透明载体（18; 24）之间的基底（10），所述基底（10） 透明层（18）连接到第二透明载体（24），导管填充有发光溶液（20）。 这有助于在这种发光组分（30）中使用量子点的胶体溶液。 优选地，使用直接晶片接合技术将衬底（10）直接接合到透明载体（18,24）。

公开(公告)号：US20120105311A1

公开(公告)日：2012-05-03

申请号：US13056116

申请日：2009-07-27

Applicant: Benoit Bataillou ,  Radu Surdeanu ,  Pascal Bancken ,  David van Steenwinckel ,  Viet Nguyen Hoang

Inventor： Benoit Bataillou ,  Radu Surdeanu ,  Pascal Bancken ,  David van Steenwinckel ,  Viet Nguyen Hoang

IPC: G09G3/00

CPC classification number: G02F1/19 ,  G02F1/0147 ,  G02F1/23 ,  G02F2203/10 ,  G09G2300/00

Abstract: A display device comprises a substrate which carries an array of pixels. Each pixel comprises an array of apertures in the substrate, each aperture of the array having a maximum opening dimension less than the wavelength of the light to be transmitted through the aperture. The effective dielectric constant of the aperture and/or the dielectric constant of the substrate is varied, thereby to vary the light transmission characteristics of the pixel between transmission of at least one frequency in the visible spectrum and transmission of substantially no frequency in the visible spectrum.

Abstract translation: 显示装置包括承载像素阵列的基板。 每个像素包括衬底中的孔阵列，阵列的每个孔具有小于要透过孔的光的波长的最大开口尺寸。 孔的有效介电常数和/或介质的介电常数发生变化，从而改变可见光谱中的至少一个频率的透射之间像素的透光特性以及可见光谱中基本上没有频率的透射 。