公开(公告)号：US07973333B2

公开(公告)日：2011-07-05

申请号：US11730514

申请日：2007-04-02

申请人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

发明人： Franz Dietz ,  Volker Dudek ,  Thomas Hoffmann ,  Michael Graf ,  Stefan Schwantes

IPC分类号： H01L29/66

CPC分类号： H01L29/66659 ,  H01L29/42368 ,  H01L29/66681 ,  H01L29/7816 ,  H01L29/7835

摘要： A lateral DMOS-transistor is provided that includes a MOS-diode made of a semi-conductor material of a first type of conductivity, a source-area of a second type of conductivity and a drain-area of a second type of conductivity which is separated from the MOS-diode by a drift region made of a semi-conductor material of a second type of conductivity which is at least partially covered by a dielectric gate layer which also covers the semi-conductor material of the MOS-diode. The dielectric gate-layer comprises a first region of a first thickness and a second region of a second thickness. The first region covers the semi-conductor material of the MOS-diode and the second region is arranged on the drift region. A transition takes place from the first thickness to the second thickness such that an edge area of the drift region which is oriented towards the MOS-diode is arranged below the second area of the gate layer. The invention also relates to a method for the production of these types of DMOS-transistors.

摘要翻译： 提供了一种横向DMOS晶体管，其包括由第一导电类型的半导体材料制成的MOS二极管，第二导电类型的源极区域和第二导电类型的漏极区域，其为 通过由第二导电类型的半导体材料制成的漂移区域与MOS二极管分开，所述漂移区域至少部分被还覆盖MOS二极管的半导体材料的介电栅极层覆盖。 介电栅极层包括第一厚度的第一区域和第二厚度的第二区域。 第一区域覆盖MOS二极管的半导体材料，第二区域布置在漂移区域上。 从第一厚度到第二厚度发生转变，使得朝向MOS二极管定向的漂移区的边缘区域布置在栅极层的第二区域的下方。 本发明还涉及一种用于生产这些类型的DMOS晶体管的方法。

公开(公告)号：US07407851B2

公开(公告)日：2008-08-05

申请号：US11386316

申请日：2006-03-22

申请人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

发明人： Gayle W. Miller ,  Irwin D. Rathbun ,  Stefan Schwantes ,  Michael Graf ,  Volker Dudek

IPC分类号： H01L21/8238 ,  H01L21/38

CPC分类号： H01L21/2253 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/7835

摘要： A method of fabricating an electronic device and a resulting electronic device. The method includes forming a pad oxide layer on a substrate, forming a silicon nitride layer over the pad oxide layer, and forming a top oxide layer over the silicon nitride layer. A first dopant region is then formed in a first portion of the substrate. A first portion of the top oxide layer is removed; a remaining portion of the top oxide layer is used to align a second dopant mask and a second dopant region is formed. An annealing step drives-in the dopants but oxygen diffusion to the substrate is limited by the silicon nitride layer; the silicon nitride layer thereby assures that the uppermost surface of the silicon is substantially planar in an area proximate to the dopant regions after the annealing step.

摘要翻译： 一种制造电子设备的方法和由此产生的电子设备。 该方法包括在衬底上形成衬垫氧化物层，在衬垫氧化物层上形成氮化硅层，并在氮化硅层上形成顶部氧化物层。 然后在衬底的第一部分中形成第一掺杂区域。 除去顶部氧化物层的第一部分; 使用顶部氧化物层的剩余部分来对准第二掺杂剂掩模，并且形成第二掺杂剂区域。 退火步骤驱动掺杂剂，但是氧化物扩散到衬底受到氮化硅层的限制; 因此，氮化硅层确保在退火步骤之后，在靠近掺杂剂区域的区域中硅的最上表面基本上是平面的。

公开(公告)号：US20080173940A1

公开(公告)日：2008-07-24

申请号：US12018721

申请日：2008-01-23

申请人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

发明人： Gayle W. Miller ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L29/78

CPC分类号： H01L29/7824 ,  H01L21/823481 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/086 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66689 ,  H01L29/7835

摘要： A method of fabricating an electronic device and the resulting electronic device. The method includes forming a gate oxide on an uppermost side of a silicon-on-insulator substrate; forming a first polysilicon layer over the gate oxide; and forming a first silicon dioxide layer over the first polysilicon layer. A first silicon nitride layer is then formed over the first silicon dioxide layer followed by a second silicon dioxide layer. Shallow trenches are etched through all preceding dielectric layers and into the SOI substrate. The etched trenches are filled with another dielectric layer (e.g., silicon dioxide) and planarized. Each of the preceding dielectric layers are removed, leaving an uppermost sidewall area of the dielectric layer exposed for contact with a later-applied polysilicon gate area. Formation of the sidewall area assures a full-field oxide thickness thereby producing a device with a reduced-electric field and a reduced capacitance between gate and drift regions.

摘要翻译： 一种制造电子装置的方法和所得到的电子装置。 该方法包括在绝缘体上硅衬底的最上侧形成栅极氧化物; 在所述栅极氧化物上形成第一多晶硅层; 以及在所述第一多晶硅层上形成第一二氧化硅层。 然后在第一二氧化硅层上形成第一氮化硅层，接着形成第二二氧化硅层。 通过所有以前的介电层蚀刻浅沟槽并进入SOI衬底。 蚀刻的沟槽用另一介质层（例如二氧化硅）填充并平坦化。 去除每个前述电介质层，留下电介质层的最上面的侧壁区域暴露以与稍后施加的多晶硅栅极区域接触。 侧壁区域的形成确保全场氧化物厚度，从而产生具有减小的电场和栅极和漂移区域之间的减小的电容的器件。

公开(公告)号：US20070120190A1

公开(公告)日：2007-05-31

申请号：US11254387

申请日：2005-10-20

申请人： Stefan Schwantes ,  Michael Graf ,  Volker Dudek ,  Gayle Miller ,  Irwin Rathbun ,  Peter Grombach ,  Manfred Klaussner

发明人： Stefan Schwantes ,  Michael Graf ,  Volker Dudek ,  Gayle Miller ,  Irwin Rathbun ,  Peter Grombach ,  Manfred Klaussner

IPC分类号： H01L23/62

CPC分类号： H01L27/0266 ,  H01L29/0696 ,  H01L29/1087 ,  H01L29/7835

摘要： An electrostatic discharge (ESD) protection structure is disclosed. The ESD protection structure comprises an active device. The active device includes a plurality of drains. Each of the drains has a contact row and at least one body contact row. The at least one body contact row is located on the active device in a manner to reduce the amount of voltage required for triggering the ESD protection structure. A system and method in accordance with the present invention utilizes a LDNMOS transistor as ESD protection element with optimised substrate contacts. The ratio of substrate contact rows to drain contact rows is smaller than one in order to reduce the triggering voltage of the inherent bipolar transistor.

摘要翻译： 公开了一种静电放电（ESD）保护结构。 ESD保护结构包括有源器件。 有源器件包括多个漏极。 每个排水沟具有接触排和至少一个身体接触排。 所述至少一个体接触排以减少触发ESD保护结构所需的电压量的方式位于有源器件上。 根据本发明的系统和方法利用LDNMOS晶体管作为具有优化的衬底接触的ESD保护元件。 为了降低固有双极晶体管的触发电压，衬底接触行与漏极接触行的比例小于1。

公开(公告)号：US20070090432A1

公开(公告)日：2007-04-26

申请号：US11254580

申请日：2005-10-20

申请人： Stefan Schwantes ,  Volker Dudek ,  Michael Graf ,  Alan Renninger ,  James Shen

发明人： Stefan Schwantes ,  Volker Dudek ,  Michael Graf ,  Alan Renninger ,  James Shen

IPC分类号： H01L29/94 ,  H01L27/108 ,  H01L29/76 ,  H01L31/119 ,  H01L21/8242

CPC分类号： H01L27/0805 ,  H01L27/0629 ,  H01L27/105 ,  H01L27/11526 ,  H01L27/11531 ,  H01L29/0653 ,  H01L29/66659

摘要： A method and system for fabricating a stacked capacitor and a DMOS transistor are disclosed. In one aspect, the method and system include providing a bottom plate, an insulator, and an additional layer including first and second plates. The insulator covers at least a portion of the bottom plate and resides between the first and second top plates and the bottom plate. The first and second top plates are electrically coupled through the bottom plate. In another aspect, the method and system include forming a gate oxide. The method and system also include providing SV well(s) after the gate oxide is provided. A portion of the SV well(s) resides under a field oxide region of the device. Each SV well includes first, second, and third implants having a sufficient energy to provide the portion of the SV well at a desired depth under the field oxide region without significant additional thermal processing. A gate, source, and drain are also provided.

摘要翻译： 公开了一种用于制造叠层电容器和DMOS晶体管的方法和系统。 一方面，该方法和系统包括提供底板，绝缘体和包括第一和第二板的附加层。 绝缘体覆盖底板的至少一部分并且位于第一和第二顶板与底板之间。 第一和第二顶板通过底板电耦合。 另一方面，该方法和系统包括形成栅极氧化物。 该方法和系统还包括在提供栅极氧化物之后提供SV阱。 SV阱的一部分位于器件的场氧化物区域的下方。 每个SV井包括具有足够能量的第一，第二和第三植入物，以在场氧化物区域下的期望深度处提供SV井的部分，而不需要显着的额外的热处理。 还提供了门，源和漏极。

公开(公告)号：US07064385B2

公开(公告)日：2006-06-20

申请号：US10946547

申请日：2004-09-20

申请人： Volker Dudek ,  Michael Graf

发明人： Volker Dudek ,  Michael Graf

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0878 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： A DMOS-transistor has a trench bordered by a drift region including two doped wall regions and a doped floor region extending along the walls and the floor of the trench. The laterally extending floor region has a dopant concentration gradient in the lateral direction. For example, the floor region includes at least two differently-doped floor portions successively in the lateral direction. This dopant gradient in the floor region is formed by carrying out at least one dopant implantation from above through the trench using at least one mask to expose a first area while covering a second area of the floor region.

摘要翻译： DMOS晶体管具有由漂移区域界定的沟槽，该漂移区域包括两个掺杂的壁区域和沿沟槽的壁和底部延伸的掺杂的地板区域。 横向延伸的地板区域在横向上具有掺杂剂浓度梯度。 例如，地板区域在横向上连续地包括至少两个不同掺杂的地板部分。 通过使用至少一个掩模通过沟槽从上方进行至少一个掺杂剂注入来形成地板区域中的该掺杂剂梯度，以在覆盖地板区域的第二区域的同时露出第一区域。

公开(公告)号：US06933215B2

公开(公告)日：2005-08-23

申请号：US10170098

申请日：2002-06-11

申请人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

发明人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

IPC分类号： H01L21/265 ,  H01L21/336 ,  H01L21/762 ,  H01L29/06 ,  H01L29/08 ,  H01L29/78 ,  H01L21/266

CPC分类号： H01L29/0847 ,  H01L21/2652 ,  H01L21/26586 ,  H01L21/76232 ,  H01L21/76237 ,  H01L29/0653 ,  H01L29/66659 ,  H01L29/7835

摘要： In a method of producing a doped semiconductor structure with a trench, it is possible to set the doping of the trench side walls independently from the doping of the trench bottom, and to set different doping concentrations of the individual trench side walls relative to each other. In the method, a mask layer with a window therein is provided on a surface of a semiconductor body, and then a first doping step, a trench etching step, and a second doping step are carried out successively through this window while this one mask layer remains in place on the surface of the semiconductor body. Further etching and doping steps can be carried out successively also through this window of the mask layer.

摘要翻译： 在制造具有沟槽的掺杂半导体结构的方法中，可以独立于沟槽底部的掺杂来设置沟槽侧壁的掺杂，并且设置各个沟槽侧壁相对于彼此的不同掺杂浓度 。 在该方法中，在半导体本体的表面上设置有具有窗口的掩模层，然后通过该窗口连续地进行第一掺杂工序，沟槽蚀刻工序和第二掺杂工序，同时将该一个掩模层 保持在半导体主体的表面上的适当位置。 进一步的蚀刻和掺杂步骤也可以通过掩模层的这个窗口连续进行。

公开(公告)号：US20050167779A1

公开(公告)日：2005-08-04

申请号：US11045382

申请日：2005-01-31

申请人： Franz Dietz ,  Volker Dudek ,  Michael Graf

发明人： Franz Dietz ,  Volker Dudek ,  Michael Graf

IPC分类号： H01L21/20 ,  H01L21/762 ,  H01L21/8238 ,  H01L21/84 ,  H01L29/76

CPC分类号： H01L21/84 ,  H01L21/823885 ,  H01L29/7812 ,  H01L29/7824

摘要： Vertically insulated active semiconductor regions having different thicknesses in an SOI wafer, which has an insulating layer, is produced. On the wafer, first active semiconductor regions having a first thickness are arranged in a layer of active semiconductor material. The second active semiconductor regions having a relatively smaller thickness are produced by epitaxial growth proceeding from at least one seed opening in a trench structure. The second semiconductor regions are substantially completely dielectrically insulated, laterally and vertically, from the first semiconductor regions by oxide layers. The width of the seed opening can be defined by lithography.

摘要翻译： 制造具有绝缘层的SOI晶片中具有不同厚度的垂直绝缘的有源半导体区域。 在晶片上，具有第一厚度的第一有源半导体区域被布置在有源半导体材料层中。 具有相对较小厚度的第二有源半导体区域通过从沟槽结构中的至少一个种子开口进行的外延生长产生。 第二半导体区域通过氧化物层从第一半导体区域基本上完全介电绝缘，横向和垂直地绝缘。 种子开口的宽度可以通过光刻来定义。

公开(公告)号：US06806131B2

公开(公告)日：2004-10-19

申请号：US10167960

申请日：2002-06-11

申请人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

发明人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

IPC分类号： H01L218238

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/1045 ,  H01L29/1095 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

公开(公告)号：US06780713B2

公开(公告)日：2004-08-24

申请号：US10167959

申请日：2002-06-11

申请人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

发明人： Christoph Bromberger ,  Franz Dietz ,  Volker Dudek ,  Michael Graf ,  Joern Herrfurth ,  Manfred Klaussner

IPC分类号： H01L21336

CPC分类号： H01L29/0886 ,  H01L21/26586 ,  H01L29/0653 ,  H01L29/0847 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/7824 ,  H01L29/7835

摘要： In a new process of making a DMOS transistor, the doping of the sloping side walls can be set independently from the doping of the floor region in a trench structure. Furthermore, different dopings can be established among the side walls. This is achieved especially by a sequence of implantation doping, etching to form the trench, formation of a scattering oxide protective layer on the side walls, and two-stage perpendicular and tilted final implantation doping. For DMOS transistors, this achieves high breakthrough voltages even with low turn-on resistances, and reduces the space requirement, in particular with regard to driver structures.

摘要翻译： 在制造DMOS晶体管的新工艺中，倾斜侧壁的掺杂可以独立于沟槽结构中底层区域的掺杂来设置。 此外，可以在侧壁之间建立不同的掺杂。 这通过一系列注入掺杂，蚀刻形成沟槽，在侧壁上形成散射氧化物保护层以及两级垂直和倾斜的最终注入掺杂来实现。 对于DMOS晶体管，即使使用低导通电阻也能实现高的突破电压，并且特别是关于驱动器结构，减少了空间需求。