公开(公告)号：US10892254B2

公开(公告)日：2021-01-12

申请号：US16409785

申请日：2019-05-11

申请人： Zhanming Li ,  Guanhou Luo ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

发明人： Zhanming Li ,  Guanhou Luo ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

IPC分类号： H01L25/07 ,  H01L23/00 ,  H01L23/498 ,  H01L23/544 ,  H01L21/48 ,  H01L25/00

摘要： Use of gallium nitride (GaN) semiconductor material for power devices is challenging due to low yield caused by high defect density on the wafer. Device layout on the wafer, chip probing, and device packaging increase the yield of large area power devices. Device dies containing a plurality of lower-power sub-devices are used to achieve high power ratings, by connecting only functional sub-devices together in the package, while being tolerant of defective sub-devices by selectively excluding the defective sub-devices. The packages and methods are particularly relevant to GaN power switching devices such as high electron mobility transistors (GaN HEMT).

公开(公告)号：US20180108743A1

公开(公告)日：2018-04-19

申请号：US15783888

申请日：2017-10-13

申请人： Zhanming Li ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

发明人： Zhanming Li ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

IPC分类号： H01L29/417 ,  H01L29/40 ,  H01L29/778

CPC分类号： H01L29/41758 ,  H01L29/401 ,  H01L29/7786 ,  H01L31/022408 ,  H01L31/1085 ,  H01L33/20 ,  H01L33/38

摘要： This invention relates to interdigitated electrodes for power electronic and optoelectronic devices where field and current distribution determine the device performance. Described are geometries based on rounded asymmetrical fingers and electrode bases of varying width. Simulations demonstrate benefits for reducing self-heating and thermal power loss, which reduces overall on-state resistance and increases reverse break down voltages.

公开(公告)号：US10939553B2

公开(公告)日：2021-03-02

申请号：US16254296

申请日：2019-01-22

申请人： Zhanming Li ,  Yan-Fei Liu ,  Yue Fu ,  Wai Tung Ng

发明人： Zhanming Li ,  Yan-Fei Liu ,  Yue Fu ,  Wai Tung Ng

IPC分类号： H01L27/18 ,  H05K1/18 ,  H01L23/31 ,  H01L23/34 ,  H01L29/20 ,  H01L29/778 ,  H05K1/02 ,  H05K1/11

摘要： A packaged GaN semiconductor device with improved heat dissipation is provided. A GaN device is packaged on a printed circuit board (PCB) with a vertical side of the device, and optionally the back side of the device, in thermal contact with the PCB. The packaging is compatible with surface mount technologies such as land grid array (LGA), ball grid array (BGA), and other formats. Thermal contact between the PCB and a vertical side of the device, and optionally the back side of the device, is made through solder. The solder used for the thermal contact may also connect a source terminal of the device, which also improves electrical stability of the device. The packaging is particularly suitable for GaN HEMT devices.

公开(公告)号：US20180218961A1

公开(公告)日：2018-08-02

申请号：US15859502

申请日：2017-12-30

申请人： Zhanming Li ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

发明人： Zhanming Li ,  Yue Fu ,  Wai Tung Ng ,  Yan-Fei Liu

IPC分类号： H01L23/367 ,  H01L29/06 ,  H01L29/417 ,  H01L23/498 ,  H01L23/538 ,  H01L25/07 ,  H01L25/18 ,  H01L23/00 ,  H01L29/20

摘要： Described herein are semiconductor devices and structures with improved power handling and heat dissipation. Embodiments are suitable for implementation in gallium nitride. Devices may be provided as individual square or diamond-shaped dies having electrode terminals at the die corners, tapered electrode bases, and interdigitated electrode fingers. Device matrix structures include a plurality of device dies arranged on a substrate in a matrix configuration with interdigitated conductors. Device lattice structures are based on a unit cell comprising a plurality of individual devices, the unit cells disposed on a chip with geometric periodicity. Also described herein are methods for implementing the semiconductor devices and structures.

公开(公告)号：US5656517A

公开(公告)日：1997-08-12

申请号：US473837

申请日：1995-06-07

申请人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

发明人： Taylor R. Efland ,  Roy C. Jones, III ,  Oh-Kyong Kwon ,  Michael C. Smayling ,  Satwinder Malhi ,  Wai Tung Ng

IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/78 ,  H01L21/265

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/7802 ,  H01L29/42368

摘要： A source cell having reduced area and reduced polysilicon window width requirements for use as the source region in a DMOS transistor is disclosed, comprising: a source region of semiconductor material disposed on a semiconductor substrate; a plurality of backgate contact segments of predetermined size and separated by predetermined distances; and a plurality of source contact windows alternating with the backgate contact segments so that a narrow source contact region is formed of alternating source contact and backgate contact material. A DMOS transistor embodying the source region including the backgate contact segments and windowed source contacting regions of the invention is disclosed. An integrated circuit providing an array of DMOS transistors having the improved source regions of the invention is disclosed.Other devices, systems and methods are also disclosed.

摘要翻译： 公开了一种具有减小的面积和降低的多晶硅窗口宽度要求的源单元，用于DMOS晶体管中的源极区域，包括：设置在半导体衬底上的半导体材料的源极区域; 多个预定尺寸的后门接触片段并隔开预定距离; 以及多个源极接触窗与后盖接触片交替，使得窄的源极接触区域由交替的源极接触和后盖接触材料形成。 公开了体现源区域的DMOS晶体管，其包括本发明的背栅接触段和窗口源极接触区域。 公开了提供具有本发明改进的源极区域的DMOS晶体管阵列的集成电路。 还公开了其他装置，系统和方法。

公开(公告)号：US20220109048A1

公开(公告)日：2022-04-07

申请号：US17487117

申请日：2021-09-28

申请人： Zhanming Li ,  Yan-Fei Liu ,  Wai Tung Ng

发明人： Zhanming Li ,  Yan-Fei Liu ,  Wai Tung Ng

IPC分类号： H01L29/06 ,  H01L29/20 ,  H01L29/778 ,  H01L29/66

摘要： A gallium nitride (GaN) semiconductor device has first and second electrodes connected to a top metal layer disposed in complementary first and second irregular shapes, each irregular shape including a wide connection area at a first end, a tapered area, and a narrow area at a second end. The first and second irregular shapes are arranged adjacent each other along complementary edges such that a gap between the complementary edges is of substantially constant width. The first and second wide connection areas include pads for wire bond or land grid array electrical connections to external circuitry. The first and second irregular shapes for source and drain metal of a field effect transistor (FET) or high electron mobility transistor (HEMT) allows the width of the gate finger to be short so that electrical current injected from the gate can reach all portions of the gate fingers efficiently during high frequency switching, making the topology suitable for high voltage power devices.

公开(公告)号：US20190379374A1

公开(公告)日：2019-12-12

申请号：US16423138

申请日：2019-05-27

申请人： Zhanming Li ,  Yan-Fei Liu ,  Yue Fu ,  Wai Tung Ng

发明人： Zhanming Li ,  Yan-Fei Liu ,  Yue Fu ,  Wai Tung Ng

IPC分类号： H03K17/30 ,  H03K17/06 ,  H03K17/22

摘要： A gate driver circuit for a gallium nitride (GaN) power transistor includes a RS-flipflop that receives a first pulse train at an S input terminal and a second pulse train at an R input terminal, and produces an output pulse train, and an amplifier that amplifies the output pulse train and produces a gate driver signal for the GaN power transistor. The RS-flipflop and the amplifier may be implemented together on a GaN monolithic integrated circuit, optionally together with the GaN power transistor. The GaN power transistor may be a high-side switch of a half-bridge circuit. The RS-flipflop may be implemented with enhancement mode and depletion mode GaN high electron mobility transistors (HEMTs). Embodiments avoid drawbacks of prior hybrid (e.g., silicon-GaN) approaches, such as parasitic inductances from bonding wires and on-board metal traces, especially at high operating frequencies, as well as reduce implementation cost and improve performance.

公开(公告)号：US08357986B2

公开(公告)日：2013-01-22

申请号：US12466396

申请日：2009-05-15

申请人： Hao Wang ,  Wai Tung Ng ,  Huaping Xu

发明人： Hao Wang ,  Wai Tung Ng ,  Huaping Xu

IPC分类号： H01L29/732

CPC分类号： H01L29/7835 ,  H01L29/0653 ,  H01L29/1083 ,  H01L29/407 ,  H01L29/4236 ,  H01L29/42376 ,  H01L29/66621 ,  H01L29/66659

摘要： An orthogonal gate extended drain MOSFET (EDMOS) structure provides a low gate-to-drain capacitance (CGD) and exhibits increased reliability. It has a gate electrode that is folded into the shallow trench isolation (STI) oxide region. Horizontal and vertical gate electrode segments provide gate control. It accommodates both high voltage devices and standard CMOS components on the same substrate. Reduced surface field (RESURF) technology is employed to optimize tradeoffs between high breakdown voltage and specific on-resistance. Device fabrication steps are compatible with standard CMOS flow and process modules can be added or removed from baseline CMOS technology.

摘要翻译： 正交栅扩展漏极MOSFET（EDMOS）结构提供了低栅极 - 漏极电容（CGD），并且表现出更高的可靠性。 它具有折叠成浅沟槽隔离（STI）氧化物区域的栅电极。 水平和垂直栅电极段提供栅极控制。 它可以在同一基板上兼容高压器件和标准CMOS器件。 采用减少的表面场（RESURF）技术来优化高击穿电压和特定导通电阻之间的折衷。 器件制造步骤与标准CMOS流程兼容，可以从基准CMOS技术中添加或删除工艺模块。

公开(公告)号：US07777562B2

公开(公告)日：2010-08-17

申请号：US12241191

申请日：2008-09-30

申请人： Guo Wen Wei ,  Wai Tung Ng

发明人： Guo Wen Wei ,  Wai Tung Ng

IPC分类号： H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/3205

摘要： A digital Class-D amplifier distortion suppression circuit design is disclosed. A distortion suppression feedback loop is described to improve audio performance by suppressing output stage non-linearity and improving power supply noise rejection achieving reduced THD+N. The feedback loop is placed around the power stage. It forces tracking between the audio band signals at the input and output of the power stage by automatically adjusting the gating signal timing based on sensed effective duty ratio error. Error sensing and compensation are performed using techniques that lend to simple circuit implementation.

摘要翻译： 公开了一种数字D类放大器失真抑制电路设计。 描述了失真抑制反馈环路，通过抑制输出级非线性度和改善电源噪声抑制来提高音频性能，从而降低THD + N。 反馈回路放置在功率级的周围。 它通过根据感测到的有效占空比误差自动调节门控信号定时来强制在功率级的输入和输出之间的音频信号之间的跟踪。 使用可简化电路实现的技术来执行误差检测和补偿。

公开(公告)号：US20090160553A1

公开(公告)日：2009-06-25

申请号：US12241191

申请日：2008-09-30

申请人： Guo Wen Wei ,  Wai Tung Ng

发明人： Guo Wen Wei ,  Wai Tung Ng

IPC分类号： H03F3/217 ,  H03F3/38

CPC分类号： H03F3/2173 ,  H03F1/3205

摘要： A digital Class-D amplifier distortion suppression circuit design is disclosed. A distortion suppression feedback loop is described to improve audio performance by suppressing output stage non-linearity and improving power supply noise rejection achieving reduced THD+N. The feedback loop is placed around the power stage. It forces tracking between the audio band signals at the input and output of the power stage by automatically adjusting the gating signal timing based on sensed effective duty ratio error. Error sensing and compensation are performed using techniques that lend to simple circuit implementation.

摘要翻译： 公开了一种数字D类放大器失真抑制电路设计。 描述了失真抑制反馈环路，通过抑制输出级非线性度和改善电源噪声抑制来提高音频性能，从而降低THD + N。 反馈回路放置在功率级的周围。 它通过根据感测到的有效占空比误差自动调节门控信号定时来强制在功率级的输入和输出之间的音频信号之间的跟踪。 使用可简化电路实现的技术来执行误差检测和补偿。