公开(公告)号：US09418876B2

公开(公告)日：2016-08-16

申请号：US13224575

申请日：2011-09-02

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/00 ,  H01L21/56 ,  H01L21/683 ,  H01L25/065 ,  H01L23/00

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US09153462B2

公开(公告)日：2015-10-06

申请号：US12964097

申请日：2010-12-09

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou

IPC: H01L21/687 ,  H01L21/67

CPC classification number: H01L21/67051 ,  H01L21/68728

Abstract: A device and system for thin wafer cleaning is disclosed. A preferred embodiment comprises a spin chuck having at least three holding clamps. A thin wafer with a wafer frame is mounted on the spin chuck through a tape layer. When the holding clamps are unlocked, there is no interference with the removal and placement of the wafer frame. On the other hand, when the holding clamps are locked, the holding clamps are brought into contact with the outer edge of the wafer frame so as to prevent the wafer frame from moving laterally. Furthermore, the shape of the holding clamps in a locked position is capable of preventing the wafer frame from moving vertically.

Abstract translation: 公开了用于薄晶片清洁的装置和系统。 优选实施例包括具有至少三个保持夹具的旋转卡盘。 具有晶片框架的薄晶片通过带层安装在旋转卡盘上。 当保持夹具解锁时，不会干扰晶片框架的移除和放置。 另一方面，当保持夹具被锁定时，保持夹具与晶片框架的外边缘接触，以防止晶片框架横向移动。 此外，保持夹具处于锁定位置的形状能够防止晶片框架垂直移动。

公开(公告)号：US08896136B2

公开(公告)日：2014-11-25

申请号：US12827563

申请日：2010-06-30

Applicant: Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Chen-Yu Tsai ,  Shih-Hui Wang ,  Chien-Ming Chiu ,  Chia-Ho Chen ,  Fang Wen Tsai ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L23/544 ,  H01L29/40 ,  H01L23/48 ,  H01L23/52 ,  H01L21/76 ,  H01L21/00 ,  H01L21/4763 ,  H01L21/44 ,  H01L21/683

CPC classification number: H01L23/481 ,  H01L21/30604 ,  H01L21/6835 ,  H01L21/76831 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/544 ,  H01L2221/68327 ,  H01L2223/54426 ,  H01L2224/13

Abstract: In accordance with an embodiment, a structure comprises a substrate having a first area and a second area; a through substrate via (TSV) in the substrate penetrating the first area of the substrate; an isolation layer over the second area of the substrate, the isolation layer having a recess; and a conductive material in the recess of the isolation layer, the isolation layer being disposed between the conductive material and the substrate in the recess.

Abstract translation: 根据实施例，结构包括具有第一区域和第二区域的基板; 穿过基板的第一区域的贯穿基板通孔（TSV）; 在所述衬底的所述第二区域上方的隔离层，所述隔离层具有凹部; 以及在所述隔离层的所述凹部中的导电材料，所述隔离层设置在所述凹部中的所述导电材料和所述基板之间。

公开(公告)号：US08846499B2

公开(公告)日：2014-09-30

申请号：US12858211

申请日：2010-08-17

Applicant: Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Ying-Ching Shih ,  Weng-Jin Wu ,  Jing-Cheng Lin ,  Wen-Chih Chiou ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/30

CPC classification number: G07F17/3213 ,  B32B17/10 ,  B32B37/1207 ,  B32B37/182 ,  B32B37/185 ,  B32B2457/14 ,  H01L21/6835 ,  H01L2221/68318 ,  H01L2221/68327 ,  H01L2221/6834 ,  H01L2221/68381

Abstract: A composite carrier structure for manufacturing semiconductor devices is provided. The composite carrier structure utilizes multiple carrier substrates, e.g., glass or silicon substrates, coupled together by interposed adhesive layers. The composite carrier structure may be attached to a wafer or a die for, e.g., backside processing, such as thinning processes. In an embodiment, the composite carrier structure comprises a first carrier substrate having through-substrate vias formed therethrough. The first substrate is attached to a second substrate using an adhesive such that the adhesive may extend into the through-substrate vias.

Abstract translation: 提供了一种用于制造半导体器件的复合载体结构。 复合载体结构利用多个载体衬底，例如玻璃或硅衬底，通过插入的粘合剂层耦合在一起。 复合载体结构可以附接到晶片或模具，用于例如背面处理，例如变薄处理。 在一个实施例中，复合载体结构包括具有贯穿其中形成的贯通基板通孔的第一载体基板。 使用粘合剂将第一衬底附接到第二衬底，使得粘合剂可以延伸到贯穿衬底通孔中。

公开(公告)号：US08722540B2

公开(公告)日：2014-05-13

申请号：US12841874

申请日：2010-07-22

Applicant: Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

Inventor： Yu-Liang Lin ,  Weng-Jin Wu ,  Jing-Cheng Lin

IPC: H01L21/302 ,  H01L21/461

CPC classification number: H01L21/6835 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: A method includes bonding a wafer on a carrier through an adhesive, and performing a thinning process on the wafer. After the step of performing the thinning process, a portion of the adhesive not covered by the wafer is removed, while the portion of the adhesive covered by the wafer is not removed.

Abstract translation: 一种方法包括通过粘合剂将晶片接合在载体上，并在晶片上进行稀化处理。 在进行稀化处理的步骤之后，去除未被晶片覆盖的粘合剂的一部分，同时由晶片覆盖的粘合剂部分未被除去。

公开(公告)号：US08486823B2

公开(公告)日：2013-07-16

申请号：US12044008

申请日：2008-03-07

Applicant: Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu ,  Jung-Chih Hu

Inventor： Wen-Chih Chiou ,  Chen-Hua Yu ,  Weng-Jin Wu ,  Jung-Chih Hu

IPC: H01L21/4763

CPC classification number: H01L23/481 ,  H01L21/76898 ,  H01L25/50 ,  H01L2225/06513 ,  H01L2225/06541 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

Abstract: A through via process is performed on a semiconductor substrate with a contact plug formed in an interlayer dielectric (ILD), and then a via plug is formed in the ILD layer to extend through a portion of the semiconductor substrate, followed forming an interconnection structure electrically connected with the contact plug and the via plug.

Abstract translation: 在具有形成在层间电介质（ILD）中的接触插塞的半导体衬底上进行通孔工艺，然后在ILD层中形成通孔以延伸穿过半导体衬底的一部分，然后电连接形成互连结构 与接触插头和通孔插头连接。

公开(公告)号：US20130171772A1

公开(公告)日：2013-07-04

申请号：US13775983

申请日：2013-02-25

Applicant: Yung-Chi LIN ,  Weng-Jin WU ,  Shau-Lin SHUE

Inventor： Yung-Chi LIN ,  Weng-Jin WU ,  Shau-Lin SHUE

IPC: H01L21/768

CPC classification number: H01L21/76871 ,  H01L21/76844 ,  H01L21/76877 ,  H01L21/76898 ,  H01L23/481 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2924/3011 ,  H01L2924/014 ,  H01L2924/00014

Abstract: In a process, an opening is formed to extend from a front surface of a semiconductor substrate through a part of the semiconductor substrate. A metal seed layer is formed on a sidewall of the opening. A block layer is formed on only a portion of the metal seed layer. A metal layer is formed on the block layer and the metal seed layer to fill the opening.

Abstract translation: 在此过程中，形成从半导体衬底的前表面延伸穿过半导体衬底的一部分的开口。 金属种子层形成在开口的侧壁上。 仅在金属种子层的一部分上形成阻挡层。 在阻挡层和金属种子层上形成金属层以填充开口。

公开(公告)号：US08432038B2

公开(公告)日：2013-04-30

申请号：US12783973

申请日：2010-05-20

Applicant: Weng-Jin Wu ,  Yung-Chi Lin ,  Wen-Chih Chiou

Inventor： Weng-Jin Wu ,  Yung-Chi Lin ,  Wen-Chih Chiou

IPC: H01L23/48

CPC classification number: H01L21/76843 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/525 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/0554 ,  H01L2224/0557 ,  H01L2224/05571 ,  H01L2224/05573 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/00013 ,  H01L2924/00014 ,  H01L2924/01012 ,  H01L2924/01025 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2224/13099 ,  H01L2924/00 ,  H01L2224/05599 ,  H01L2224/0555 ,  H01L2224/0556

Abstract: A through-silicon via (TSV) structure and process for forming the same are disclosed. A semiconductor substrate has a front surface and a back surface, and a TSV structure is formed to extend through the semiconductor substrate. The TSV structure includes a metal layer, a metal seed layer surrounding the metal layer, a barrier layer surrounding the metal seed layer, and a metal silicide layer formed in a portion sandwiched between the metal layer and the metal seed layer.

Abstract translation: 公开了一种贯穿硅通孔（TSV）结构及其形成方法。 半导体衬底具有前表面和后表面，并且形成TSV结构以延伸穿过半导体衬底。 TSV结构包括金属层，围绕金属层的金属籽晶层，围绕金属籽晶层的阻挡层和形成在夹在金属层和金属籽晶层之间的部分中的金属硅化物层。

公开(公告)号：US20130056865A1

公开(公告)日：2013-03-07

申请号：US13224575

申请日：2011-09-02

Applicant: Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

Inventor： Jing-Cheng Lin ,  Weng-Jin Wu ,  Shih Ting Lin ,  Cheng-Lin Huang ,  Szu Wei Lu ,  Shin-Puu Jeng ,  Chen-Hua Yu

IPC: H01L21/78 ,  H01L23/498

CPC classification number: H01L21/78 ,  H01L21/561 ,  H01L21/563 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L24/16 ,  H01L25/0652 ,  H01L2221/68327 ,  H01L2224/16235 ,  H01L2224/73204 ,  H01L2224/81005 ,  H01L2224/81193 ,  H01L2224/97 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2224/81

Abstract: A method of fabricating a three-dimensional integrated circuit comprises attaching a wafer to a carrier, mounting a plurality of semiconductor dies on top of the wafer to form a wafer stack. The method further comprises forming a molding compound layer on top of the wafer, attaching the wafer stack to a tape frame and dicing the wafer stack to separate the wafer stack into a plurality of individual packages.

Abstract translation: 制造三维集成电路的方法包括将晶片附着到载体上，将多个半导体管芯安装在晶片的顶部上以形成晶片堆叠。 该方法还包括在晶片的顶部上形成模塑复合层，将晶片堆叠连接到胶带框架上，并切割晶片堆叠以将晶片堆叠分离成多个单独的封装。

公开(公告)号：US08252682B2

公开(公告)日：2012-08-28

申请号：US12704695

申请日：2010-02-12

Applicant: Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

Inventor： Ku-Feng Yang ,  Weng-Jin Wu ,  Hsin-Hsien Lu ,  Chia-Lin Yu ,  Chu-Sung Shih ,  Fu-Chi Hsu ,  Shau-Lin Shue

IPC: H01L21/44 ,  H01L23/48

CPC classification number: H01L21/76898 ,  H01L2224/02372

Abstract: A method for thinning a wafer is provided. In one embodiment, a wafer is provided having a plurality of semiconductor chips, the wafer having a first side and a second side opposite the first side, wherein each of the chips includes a set of through silicon vias (TSVs), each of the TSVs substantially sealed by a liner layer and a barrier layer. A wafer carrier is provided for attaching to the second side of the wafer. The first side of the wafer is thinned and thereafer recessed to partially expose portions of the liner layers, barrier layers and the TSVs protruding from the wafer. An isolation layer is deposited over the first side of the wafer and the top portions of the liner layers, barrier layers and the TSVs. Thereafter, an insulation layer is deposited over the isolation layer. The insulation layer is then planarized to expose top portions of the TSVs. A dielectric layer is deposited over the planarized first side of the wafer. One or more electrical contacts are formed in the dielectric layer for electrical connection to the exposed one or more TSVs.

Abstract translation: 提供了一种用于薄化晶片的方法。 在一个实施例中，提供具有多个半导体芯片的晶片，晶片具有第一侧和与第一侧相对的第二侧，其中每个芯片包括一组穿通硅通孔（TSV），每个TSV 基本上被衬垫层和阻挡层密封。 提供晶片载体以附接到晶片的第二侧。 晶片的第一侧变薄并且凹陷以部分地暴露衬里层，阻挡层和从晶片突出的TSV的部分。 隔离层沉积在晶片的第一侧和衬垫层，阻挡层和TSV的顶部之上。 此后，绝缘层沉积在隔离层上。 然后将绝缘层平坦化以暴露TSV的顶部。 电介质层沉积在晶片的平坦化第一侧上。 在电介质层中形成一个或多个电触头，用于与暴露的一个或多个TSV电连接。