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公开(公告)号：US08356124B1
公开(公告)日：2013-01-15
申请号：US10846386
申请日：2004-05-14
IPC分类号： G06F3/00 , G06F5/00 , G06F13/368 , G06F13/14 , H04L12/40
CPC分类号： G06F13/362
摘要： A data transfer system includes a PCI Express transaction layer having an input for serially receiving posted and non-posted request packets and completion packets; an application layer coupled to the PCI Express transaction layer for receiving posted and non-posted request packets and completion packets from the PCI Express transaction layer; a first transmission interface coupling the application layer to the PCI Express transaction layer; and a second transmission interface coupling the application layer to the PCI Express transaction layer. The PCI Express transaction layer transmits posted and non-posted request packets to the application layer over the first transmission interface and transmits completion packets to the application layer over the second transmission interface.
摘要翻译： 数据传输系统包括具有用于串行接收发布和未发布的请求分组和完成分组的输入的PCI Express事务层; 耦合到PCI Express事务层的应用层，用于从PCI Express事务层接收发布和未发布的请求分组和完成分组; 将应用层耦合到PCI Express事务层的第一传输接口; 以及将应用层耦合到PCI Express事务层的第二传输接口。 PCI Express事务层通过第一传输接口将发布和未发布的请求数据包发送到应用层，并通过第二个传输接口将完成数据包发送到应用层。
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2.发明授权Data storage system having CPUs adapted to perform a second atomic operation request prior to completion of a first atomic operation request 有权具有适于在完成第一原子操作请求之前执行第二原子操作请求的CPU的数据存储系统公开(公告)号：US07769928B1
公开(公告)日：2010-08-03
申请号：US11769743
申请日：2007-06-28
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07729239B1
公开(公告)日：2010-06-01
申请号：US11022998
申请日：2004-12-27
IPC分类号： G01R31/08 , G06F11/00 , G08C15/00 , H04J1/16 , H04J3/14 , H04L1/00 , H04L12/26 , H04L12/28 , H04L12/56 , H04L12/54
CPC分类号： H04L45/00 , H04L1/1874 , H04L45/302 , H04L45/40
摘要： An end point controller includes two of ingress/egress port pairs. A first one of the ingress/egress ports is adapted to send and receive one of a pair of types of information packets and a second one of the ingress/egress ports is adapted to send and receive the other one of the pair of types of information packets. A controller is coupled to the two port pairs for coupling one of ingress/egress ports to an input/output port selectively in accordance with the type of the information packet on the ingress/egress ports and the availability of the end point controller to a network. One of the egress ports is directly coupled to the output port to the network if the information packet is at such port and the end point controller has been granted access to the network while other information at the pair of egress ports is buffered prior to being coupled to the output. In like fashion, the input port from the network is directly coupled to one of the ingress ports if the information packet is of the type of information packet destined for such ingress port, said port being available to transmit the packet.
摘要翻译： 端点控制器包括入口/出口端口对中的两个。 入口/出口端口中的第一个适于发送和接收一对类型的信息分组中的一个，并且入口/出口端口中的第二个适于发送和接收一对类型的信息中的另一个 数据包 控制器耦合到两个端口对，以根据入口/出口端口上的信息分组的类型选择性地将输入/输出端口中的一个端口耦合到输入/输出端口，以及端点控制器到网络的可用性 。 如果信息分组处于这样的端口，则出口端口之一直接耦合到网络的输出端口，并且端点控制器已经被授权接入网络，而在对耦合端口的其他信息被耦合之前被缓冲 到输出。 如果信息分组是目的地为这样的入口端口的信息分组的类型，则来自网络的输入端口直接耦合到入口端口之一，所述端口可用于传送分组。
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4.发明授权Data storage system having separate atomic operation/non-atomic operation paths 有权数据存储系统具有单独的原子操作/非原子操作路径公开(公告)号：US07707367B1
公开(公告)日：2010-04-27
申请号：US11769739
申请日：2007-06-28
CPC分类号： G06F13/4054
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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5.发明授权Data transfer method wherein a sequence of messages update tag structures during a read data transfer 有权数据传输方法，其中消息序列在读取数据传输期间更新标签结构公开(公告)号：US07231492B2
公开(公告)日：2007-06-12
申请号：US10740219
申请日：2003-12-18
CPC分类号： G06F12/0868 , G06F3/061 , G06F3/0659 , G06F3/067 , G06F12/0811 , G06F12/0813 , G06F12/0815 , G06F2212/284
摘要： A data storage system wherein a data controlling director examines the contents of the tag to determine whether requested read data exists in a local cache memory having this data controlling director or in some other local memory cache, or in a disk drive coupled to this data controlling director; and if the requested read data does exist in the local cache memory having this data controlling director, or in the disk drive coupled to director; the data controlling director sends a copy to the local cache memory of the read request receiving director; updates its tag to show a shared copy will reside in the requesting director's local cache memory; and also sends a message to the read requesting director indicating the data is available for storage in the local cache memory on said one of the plurality of first director/memory boards having the read request receiving director.
摘要翻译： 一种数据存储系统，其中数据控制指令器检查标签的内容，以确定所请求的读取数据是否存在于具有该数据控制指令器的本地高速缓冲存储器中，或者在一些其它本地存储器高速缓存中，或与耦合到该数据控制的盘驱动器中 导向器; 并且如果所请求的读取数据确实存在于具有该数据控制指令的本地高速缓冲存储器中，或者与耦合到控制器的磁盘驱动器中; 数据控制指导者将拷贝发送到读请求接收总监的本地缓存存储器; 更新其标签以显示共享副本将驻留在请求主任的本地缓存中; 并且还向读取请求指导者发送指示数据可用于存储在具有读请求接收指导的多个第一导向器/存储器板中的所述本地高速缓冲存储器中的消息。
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公开(公告)号：US08806123B1
公开(公告)日：2014-08-12
申请号：US12569683
申请日：2009-09-29
CPC分类号： G06F3/0689 , G06F3/0626 , G06F3/0658 , G06F3/067
摘要： A data storage system having a plurality of disk drive sections, each one of the disk drive sections having a plurality of disk drives. Each one of a plurality of secondary SAS expanders is coupled to a corresponding one of the disk drive sections. Each one of the secondary SAS expanders has: (1) a plurality of first ports each one being connected to a corresponding one of the disk drives in the corresponding one of the plurality of disk drive sections coupled thereto; and (2) a second port. A main SAS expander has: (1) a first port; and (2) N second ports, each one of the N second ports of the main expander being connected to the second port of a corresponding one of the plurality of N secondary expanders. A storage processor is coupled to the second port of the main SAS expander.
摘要翻译： 一种数据存储系统，具有多个盘驱动部，每个盘驱动部具有多个盘驱动器。 多个次级SAS扩展器中的每一个耦合到相应的一个盘驱动器部分。 辅助SAS扩展器中的每一个具有：（1）多个第一端口，每个第一端口连接到与其耦合的多个盘驱动器部分中的对应的一个中的对应的一个盘驱动器; 和（2）第二个端口。 主要的SAS扩展器有：（1）第一个端口; 和（2）N个第二端口，主扩展器的N个第二端口中的每一个连接到多个N个次级扩展器中的相应一个的第二端口。 存储处理器耦合到主SAS扩展器的第二端口。
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公开(公告)号：US07987229B1
公开(公告)日：2011-07-26
申请号：US11769744
申请日：2007-06-28
申请人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
发明人： Jeffrey Kinne , John O'Shea , Michael Sgrosso , William F. Baxter, III , Christopher S. MacLellan
CPC分类号： G06F13/385 , G06F3/0658 , G06F13/28 , H04L67/1097
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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8.发明授权Data storage system having acceleration path for congested packet switching network 有权数据存储系统具有拥塞分组交换网络的加速路径公开(公告)号：US07979588B1
公开(公告)日：2011-07-12
申请号：US11769740
申请日：2007-06-28
CPC分类号： G06F13/387 , G06F2213/0026
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller passes a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的快速IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE终点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下通过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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公开(公告)号：US07672303B1
公开(公告)日：2010-03-02
申请号：US11059885
申请日：2005-02-17
CPC分类号： H04L49/505 , H04L49/205 , H04L49/356
摘要： A method is provided for performing arbitration in an information packet controller. The method includes transmitting different types of information packets from an initiator to a receiver. One type of information packet has a quality of service requiring a faster transmission time from the initiator to the receiver than another type of information packet having a quality of service having a slower transmission time from the initiator to the receiver. The transmitting of the information packets from the initiator to the receiver is in accordance with priority assigned to the information packet, the quality of service assigned to the information packet, and the age of such information packets having been stored in a queue of the initiator, such quality of service being a function of the speed at which the packets are required to pass from the initiator to a receiver.
摘要翻译： 提供了一种在信息包控制器中执行仲裁的方法。 该方法包括从发起者向接收者发送不同类型的信息分组。 一种类型的信息包具有从发起者到接收者的更快传输时间的服务质量，而不是具有从发起者到接收者的传输时间较慢的具有服务质量的信息包。 从发起者到接收者的信息包的发送是根据分配给信息包的优先级，分配给信息包的服务质量以及已经存储在发起者的队列中的信息包的年龄， 这种服务质量是要求分组从发起者到接收者的速度的函数。
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公开(公告)号：US07631128B1
公开(公告)日：2009-12-08
申请号：US11769747
申请日：2007-06-28
申请人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
发明人： Michael Sgrosso , William F. Baxter, III , Jeffrey Kinne , Christopher S. MacLellan , John O'Shea
CPC分类号： G06F13/387 , G06F3/06 , G06F2213/0026 , H04L12/56
摘要： A data storage system having protocol controller for converting packets between PCIE format used by a storage processor and Rapid IO format used by a packet switching network. The controller includes a PCIE end point for transferring atomic operation (DSA) requests, a data pipe section having a plurality of data pipes for passing user data; and a message engine section for passing messages among the plurality of storage processors. An acceleration path controller bypasses a DSA buffer in the absence of congestion on the network. Packets fed to the PCIE end point include an address portion having code indicating an atomic operation. An encoder converts the code from a PCIE format into the same atomic operation in SRIO format. Each one of a plurality of CPUs is adapted to perform a second DSA request during execution of a first DSA request.
摘要翻译： 一种具有协议控制器的数据存储系统，用于在由存储处理器使用的PCIE格式和分组交换网使用的Rapid IO格式之间转换分组。 控制器包括用于传送原子操作（DSA）请求的PCIE端点，具有用于传递用户数据的多个数据管道的数据管段; 以及用于在多个存储处理器之间传递消息的消息引擎部分。 加速路径控制器在没有网络拥塞的情况下绕过DSA缓冲区。 馈送到PCIE端点的分组包括具有指示原子操作的代码的地址部分。 编码器将代码从PCIE格式转换为与SRIO格式相同的原子操作。 多个CPU中的每一个适于在执行第一DSA请求期间执行第二DSA请求。
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