公开(公告)号：US20050208748A1

公开(公告)日：2005-09-22

申请号：US10708649

申请日：2004-03-17

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/48 ,  H01L23/485

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。

公开(公告)号：US06892925B2

公开(公告)日：2005-05-17

申请号：US10246282

申请日：2002-09-18

申请人： Mario Interrante ,  Mukta G. Farooq ,  William Sablinski

发明人： Mario Interrante ,  Mukta G. Farooq ,  William Sablinski

IPC分类号： B23K1/00 ,  B23K35/14 ,  B23K35/26 ,  B23K101/40 ,  B23K101/42 ,  C22C13/00 ,  H05K3/34 ,  H01L21/44

CPC分类号： B23K1/0016 ,  B23K35/262 ,  B23K2101/36 ,  H01L2224/16225 ,  H05K3/3436 ,  H05K3/3463 ,  H05K2201/10992 ,  H05K2203/041 ,  H05K2203/0415 ,  Y02P70/613

摘要： A lead free solder hierarchy for use in the second level solder connection of electronic components such as joining an electronic module to a circuit board. An off-eutectic solder concentration of SnCu or SnAg is used for the module side connection. This off-eutectic solder contains sufficient intermetallics to provide the module side connection with a robust second level assembly and rework process. The off-eutectic composition provides an inter-metallic phase structure in the module side fillet during assembly. The inter-metallic phase structure eliminates problems of tilt and collapse during second level assembly and aids in rework by providing a more cohesive joint allowing removal of the columns from the board without simultaneous removal from the module.

摘要翻译： 一种无铅焊料层次结构，用于电子部件的二级焊接，例如将电子模块连接到电路板。 SnCu或SnAg的脱共晶焊料浓度用于模块侧连接。 该非共晶焊料包含足够的金属间化合物，以使模块侧连接具有坚固的二级组件和返工工艺。 脱共晶组合物在组装期间在模块侧圆角中提供金属间相结构。 金属间相结构消除了在第二级组装期间的倾斜和塌陷的问题，并且通过提供更粘合的接合来帮助返工，从而允许从板上移除柱而不同时从模块移除。

公开(公告)号：US20050106059A1

公开(公告)日：2005-05-19

申请号：US10991581

申请日：2004-11-18

申请人： Mukta Farooq ,  Mario Interrante ,  William Sablinski

发明人： Mukta Farooq ,  Mario Interrante ,  William Sablinski

IPC分类号： B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34

CPC分类号： H01L21/6835 ,  B23K35/262 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

公开(公告)号：US06854636B2

公开(公告)日：2005-02-15

申请号：US10314498

申请日：2002-12-06

申请人： Mukta G. Farooq ,  Mario Interrante ,  William Sablinski

发明人： Mukta G. Farooq ,  Mario Interrante ,  William Sablinski

IPC分类号： B23K35/26 ,  C22C13/00 ,  H01L21/56 ,  H01L21/60 ,  H01L21/68 ,  H01L23/31 ,  H01L23/485 ,  H01L23/498 ,  H05K3/28 ,  H05K3/34 ,  B23K31/00

CPC分类号： H01L21/6835 ,  B23K35/262 ,  B23K2101/40 ,  H01L21/563 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49866 ,  H01L24/11 ,  H01L24/16 ,  H01L24/81 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/056 ,  H01L2224/11003 ,  H01L2224/11334 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/13111 ,  H01L2224/16 ,  H01L2224/73203 ,  H01L2224/73253 ,  H01L2224/81024 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01024 ,  H01L2924/01027 ,  H01L2924/01029 ,  H01L2924/0103 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/0105 ,  H01L2924/01051 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/15311 ,  H01L2924/15787 ,  H01L2924/181 ,  H05K3/3463 ,  H01L2924/00014 ,  H01L2924/00

摘要： An electronic package having a solder interconnect liquidus temperature hierarchy to limit the extent of the melting of the C4 solder interconnect during subsequent second level join/assembly and rework operations. The solder hierarchy employs the use of off-eutectic solder alloys of Sn/Ag and Sn/Cu with a higher liquidus temperature for the C4 first level solder interconnections, and a lower liquidus temperature alloy for the second level interconnections. When the second level chip carrier to PCB join/assembly operations occur, the chip to chip carrier C4 interconnections do not melt completely. They continue to have a certain fraction of solids, and a lower fraction of liquids, than a fully molten alloy. This provides reduced expansion of the solder join and consequently lower stresses on the C4 interconnect.

摘要翻译： 具有焊料互连液相线温度层级的电子封装，以在随后的第二级连接/组装和返工操作期间限制C4焊料互连的熔化程度。 焊料层次采用对于C4第一级焊料互连使用具有较高液相线温度的Sn / Ag和Sn / Cu的非共晶焊料合金，以及用于第二级互连的较低液相线温度合金。 当第二级芯片载体与PCB连接/组装操作发生时，芯片到芯片载体C4互连不会完全熔化。 与完全熔融的合金相比，它们仍然具有一定比例的固体和较低部分的液体。 这提供了焊料接合的减小的膨胀，并因此降低了C4互连上的较低应力。

公开(公告)号：US20060009022A1

公开(公告)日：2006-01-12

申请号：US11162468

申请日：2005-09-12

申请人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

发明人： Kamalesh Srivastava ,  Subhash Shinde ,  Tien-Jen Cheng ,  Sarah Knickerbocker ,  Roger Quon ,  William Sablinski ,  Julie Biggs ,  David Eichstadt ,  Jonathan Griffith

IPC分类号： H01L21/44

CPC分类号： H01L24/11 ,  H01L24/03 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0347 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/05001 ,  H01L2224/05022 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05124 ,  H01L2224/05147 ,  H01L2224/05556 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/1147 ,  H01L2224/13006 ,  H01L2224/13007 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01019 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/01327 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/19043 ,  H01L2924/351 ,  Y02P80/30 ,  H01L2924/00 ,  H01L2224/13 ,  H01L2924/00014

摘要： A method for forming an interconnect structure for a semiconductor device includes defining a via in a passivation layer so as expose a top metal layer in the semiconductor device. A seed layer is formed over the passivation layer, sidewalls of the via, and the top metal layer. A barrier layer is formed over an exposed portion of the seed layer, the exposed portion defined by a first patterned opening. The semiconductor device is annealed so as to cause atoms from the barrier layer to diffuse into the seed layer thereunderneath, wherein the annealing causes diffused regions of the seed layer to have an altered electrical resistivity and electrode potential with respect to undiffused regions of the seed layer.

摘要翻译： 用于形成半导体器件的互连结构的方法包括在钝化层中限定通孔，以暴露半导体器件中的顶部金属层。 在钝化层，通孔的侧壁和顶部金属层上形成种子层。 在种子层的暴露部分上形成阻挡层，暴露部分由第一图案化开口限定。 半导体器件被退火以使来自阻挡层的原子扩散到其中的晶种层中，其中退火使种子层的扩散区域相对于种子层的未扩散区域具有改变的电阻率和电极电位 。