公开(公告)号：US20120057411A1

公开(公告)日：2012-03-08

申请号：US12876560

申请日：2010-09-07

申请人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

发明人： Siegmar Koeppe ,  Winfried Kamp ,  Julie Aunis

IPC分类号： G11C7/10 ,  G11C29/00

CPC分类号： G11C29/10 ,  G11C7/10 ,  G11C11/41 ,  G11C19/28 ,  G11C29/022 ,  G11C29/32

摘要： A latch based memory device includes a plurality of latches and a method of testing the latch based memory device that includes serially connecting the latches with each other so as to form a shift register chain. A bit sequence is input into the shift register chain to shift the bit sequence through the shift register chain. A bit sequence is outputted and shifted through the shift register chain, and the input bit sequence is compared with the output sequence to evaluate the functionality of the latches in a first test phase and to test the remaining structures of the latch based memory device in a second test phase by using, e.g., a conventional scan test approach.

摘要翻译： 一种基于锁存器的存储器件包括多个锁存器和一种测试基于锁存器的存储器件的方法，该存储器件包括将锁存器彼此串联连接以形成移位寄存器链。 一个位序列被输入到移位寄存器链中，以通过移位寄存器链来移位比特序列。 输出比特序列并通过移位寄存器链进行移位，并将输入比特序列与输出序列进行比较，以评估第一个测试阶段的锁存器的功能，并测试基于锁存器的存储器件的剩余结构 通过使用例如常规扫描测试方法的第二测试阶段。

公开(公告)号：US07881465B2

公开(公告)日：2011-02-01

申请号：US11461935

申请日：2006-08-02

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth

IPC分类号： H04L9/28

CPC分类号： H03K19/0963 ,  G06F21/755 ,  H04L9/003 ,  H04L2209/046 ,  H04L2209/12

摘要： Circuit for calculating a logic combination of two encrypted input operands recieves first and second dual-rail signals comprising data values in a calculation cycle and precharge values in a precharge cycle, and receives a dual-rail encryption signal comprising encryption values in the calculation cycle and precharge values in the precharge cycle, and outputs a dual-rail result signal comprising encrypted result values in the calculation cycle and precharge values in the precharge cycle. The data and encrypted result values are encrypted with the encryption values of the dual-rail encryption signal according to an encryption rule. A logic circuit determines the encrypted result values according to the logic combination from the data and encryption values, and outputs the encrypted result values in the calculation cycle. A precharge circuit impresses precharge values when precharge values are sensed at a single input, or stops impressing the precharge values only when the first and second dual-rail signals comprise data values and the dual-rail encryption signal comprises encryption values.

摘要翻译： 用于计算两个加密输入操作数的逻辑组合的电路接收包括计算周期中的数据值和预充电周期中的预充电值的第一和第二双轨信号，并且接收包括计算周期中的加密值的双轨加密信号，以及 在预充电循环中预充电值，并且在计算周期中输出包括加密结果值的双轨结果信号和预充电循环中的预充电值。 数据和加密结果值根据加密规则用双轨加密信号的加密值进行加密。 逻辑电路根据来自数据和加密值的逻辑组合确定加密结果值，并在计算周期中输出加密的结果值。 当在单个输入端检测到预充电值时，预充电电路给予预充电值，或者仅当第一和第二双轨信号包括数据值并且双轨加密信号包括加密值时停止施加预充电值。

公开(公告)号：US20090079023A1

公开(公告)日：2009-03-26

申请号：US11860413

申请日：2007-09-24

申请人： Joerg Berthold ,  Winfried Kamp ,  Fritz Rothacher

发明人： Joerg Berthold ,  Winfried Kamp ,  Fritz Rothacher

IPC分类号： H01L21/66 ,  G06F17/50 ,  H01L27/00

CPC分类号： H01L27/0207 ,  H01L21/823807 ,  H01L27/11803 ,  H01L29/7843

摘要： A method of fabricating an integrated circuit including arranging a plurality of cells to form a desired floor plan of the integrated circuit, wherein each cell comprises at least one transistor, forming a plurality of circuit constituents from the plurality of cells of the floor plan, wherein each circuit constituent comprises at least one cell and belongs to one of a plurality circuit constituent types, and applying mechanical stress to channel regions of the at least one transistor of each cell based on the circuit constituent type of the circuit constituent to which the cell belongs.

摘要翻译： 一种制造集成电路的方法，包括布置多个单元以形成集成电路的所需平面图，其中每个单元包括至少一个晶体管，从平面图的多个单元形成多个电路组件，其中 每个电路组件包括至少一个小区，属于多个电路组成类型中的一个，并且基于小区所属的电路组件的电路组成类型，对每个小区的至少一个晶体管的沟道区域施加机械应力 。

公开(公告)号：US07492187B2

公开(公告)日：2009-02-17

申请号：US11437421

申请日：2006-05-19

申请人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

发明人： Winfried Kamp ,  Siegmar Koeppe ,  Michael Scheppler

IPC分类号： H03K19/177

CPC分类号： H03K19/17748 ,  H03K19/1776

摘要： A circuit arrangement for supplying configuration data in an FPGA device includes a plurality of output flip flops allocated to respective configurable logic cells of the FGPGA device. Each output flip flop comprises at least one data input and one data output and a data input of a first output flip flop of the plurality of output flip flops is switchably connected to a data output of a second output flip flop of the plurality of output flip flops for forming a shift register by means of a switching device integrated in the FPGA device.

摘要翻译： 用于在FPGA器件中提供配置数据的电路装置包括分配给FGPGA器件的各个可配置逻辑单元的多个输出触发器。 每个输出触发器包括至少一个数据输入和一个数据输出，并且多个输出触发器的第一输出触发器的数据输入可切换地连接到多个输出触发器的第二输出触发器的数据输出 用于通过集成在FPGA器件中的开关器件形成移位寄存器。

公开(公告)号：US07487198B2

公开(公告)日：2009-02-03

申请号：US10961521

申请日：2004-10-08

申请人： Joel Hatsch ,  Winfried Kamp

发明人： Joel Hatsch ,  Winfried Kamp

IPC分类号： G06F7/50

CPC分类号： G06F7/607 ,  H03K19/215 ,  H03K19/23

摘要： The invention relates to an adder for adding at least four bits of the same significance w, said adder having a first number of inputs for receiving the bits of the same significance w that are to be added and a number of outputs, the bits to be added being applied to the inputs in presorted form, and the adder adding the bits while taking account of the presorting. The invention also provides an adding device for adding at least four bits of equal significance and a corresponding method.

摘要翻译： 本发明涉及一种加法器，用于将相同含义w的至少四个比特相加，所述加法器具有第一数量的输入，用于接收与要相加的相同含义w的比特和多个输出， 以预分解形式将其应用于输入，加法器在考虑到预分频时加入位。 本发明还提供了一种用于添加至少四位具有相同重要性的添加装置和相应的方法。

公开(公告)号：US07342423B2

公开(公告)日：2008-03-11

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/20 ,  H03K19/094 ,  H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。

公开(公告)号：US20070035332A1

公开(公告)日：2007-02-15

申请号：US11463190

申请日：2006-08-08

申请人： Antoine Degrendel ,  Winfried Kamp

发明人： Antoine Degrendel ,  Winfried Kamp

IPC分类号： H03K19/096

CPC分类号： H03K19/0963 ,  G06F21/70

摘要： A circuit for calculating a logical combination of two input operands includes a first input for receiving a first dual rail signal having data values of the first input in a calculation cycle and precharge values in a precharge cycle, a second input for receiving a second dual rail signal having data values of the second input in the calculation cycle and precharge values in the precharge cycle, and an output for outputting a third dual rail signal having result values in the calculation cycle and precharge values in the precharge cycle. Furthermore, the circuit has a logic circuit for determining the result values according to the logical combination from the data values of the first input and the second input and for outputting the result values in the calculation cycle at the output, and a precharge circuit designed to impress precharge values in the output already when precharge values are detected at a single input, or designed to terminate impressing the precharge values only when the first dual rail signal and the second dual rail signal have data values.

摘要翻译： 用于计算两个输入操作数的逻辑组合的电路包括：第一输入，用于接收在计算周期中具有第一输入的数据值的第一双轨信号和预充电周期中的预充电值，用于接收第二双轨的第二输入 信号，其具有计算周期中的第二输入的数据值和预充电周期中的预充电值，以及用于输出在预充电周期中具有计算周期中的结果值和预充电值的第三双轨信号的输出。 此外，电路具有逻辑电路，用于根据来自第一输入和第二输入的数据值的逻辑组合确定结果值，并输出输出端的计算周期中的结果值;以及预充电电路，设计成 当在单个输入端检测到预充电值时，已经输出了输出中的预充电值，或者仅在第一双轨信号和第二双轨信号具有数据值时终止给预充电值施加压力的预充电值。

公开(公告)号：US20060294178A1

公开(公告)日：2006-12-28

申请号：US11203445

申请日：2005-08-12

申请人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

发明人： Marc Bernhardt ,  Joel Hatsch ,  Winfried Kamp ,  Siegmar Koeppe

IPC分类号： G06F7/50

CPC分类号： G06F7/607 ,  G06F7/509 ,  G06F7/5318 ,  G06F2207/3872

摘要： A carry-ripple adder having inputs for supplying three input bits of equal significance 2n that are to be summed and two carry bits of equal significance 2n+1 that are also to be summed. A calculated sum bit of significance 2n and two calculated carry bits of equal significance 2n+1 which are higher than the significance 2n of the sum bit are provided at outputs. A final carry-ripple stage VMA may be used even after a reduction to three bits.

摘要翻译： 具有输入的输入纹波加法器，其具有用于提供要求和的三个等号有效值的输入比特和两个相等重要性的两个进位比特2 n + 1，也是 被总结。 计算出的有效值的和位2＆lt; n＆gt;和两个具有相同重要性的计算的进位位2＆lt; n + 1＆lt; / 2＆gt;其高于 在输出端提供和位。 即使在减少到三位之后，也可以使用最终的进位纹波级VMA。

公开(公告)号：US20050094477A1

公开(公告)日：2005-05-05

申请号：US10943701

申请日：2004-09-17

申请人： Joel Hatsch ,  Winfried Kamp ,  Thomas Kunemund ,  Holger Sedlak ,  Heinz Soldner

发明人： Joel Hatsch ,  Winfried Kamp ,  Thomas Kunemund ,  Holger Sedlak ,  Heinz Soldner

IPC分类号： G11C15/04 ,  G11C8/02

CPC分类号： G11C15/04

摘要： One embodiment provides a content addressable memory cell having a first memory cell which is electrically connected to a comparator unit. The comparator unit is constructed from at least eight transistors, at least four transistors being arranged in a first circuit part and at least four transistors being arranged in a second circuit part and each of the circuit parts having at least two circuit branches.

公开(公告)号：US07876893B2

公开(公告)日：2011-01-25

申请号：US11462144

申请日：2006-08-03

申请人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

发明人： Antoine Degrendel ,  Winfried Kamp ,  Manfred Roth ,  Thomas Kodytek

IPC分类号： H04L9/28

CPC分类号： H03K19/0948 ,  G06F7/00 ,  G06F21/755 ,  G06F2207/7238 ,  G06F2207/7266

摘要： A logic circuit for calculating an encrypted dual-rail result operand from encrypted dual-rail input operands according to a combination rule includes inputs for receiving the input operands and an output for outputting the encrypted result operand. Each operand may comprise a first logic state or a second logic state. The logic circuit comprises a first logic stage connected between the inputs and an intermediate node and a second logic stage connected between the intermediate node and the output. The logic stages are formed to calculate the first or second logic state of the encrypted result operand from the input operands according to the combination rule and to maintain or change exactly once the logic state of the encrypted result operand, independently of an order of arrival of the encrypted input operands, depending on the combination rule, in order to impress the calculated first logic state or second logic state on the output.

摘要翻译： 用于根据组合规则从加密的双轨输入操作数计算加密的双轨结果操作数的逻辑电路包括用于接收输入操作数的输入和用于输出加密结果操作数的输出。 每个操作数可以包括第一逻辑状态或第二逻辑状态。 逻辑电路包括连接在输入与中间节点之间的第一逻辑级和连接在中间节点与输出之间的第二逻辑级。 逻辑级被形成为根据组合规则从输入操作数计算加密结果操作数的第一或第二逻辑状态，并且只要一旦加密结果操作数的逻辑状态独立于维护或更改 加密的输入操作数，取决于组合规则，以便将计算出的第一逻辑状态或第二逻辑状态置于输出上。