公开(公告)号：US08010765B2

公开(公告)日：2011-08-30

申请号：US11775780

申请日：2007-07-10

申请人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

发明人： Joo-Sun Choi ,  Won-Chang Jung ,  Hi-Choon Lee ,  Sung-Min Yim ,  Chul-Woo Park ,  Won-Il Bae

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

摘要翻译： 在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。 半导体存储器件可以包括控制单元和等待时间控制单元。 控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。 延迟控制单元可以响应于等待时间控制信号来控制等待时间值。 半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

公开(公告)号：US20100059856A1

公开(公告)日：2010-03-11

申请号：US12585133

申请日：2009-09-04

申请人： Sung-hoon Kim ,  Won-Il Bae

发明人： Sung-hoon Kim ,  Won-Il Bae

IPC分类号： H01L27/06 ,  G06F17/50

CPC分类号： H01L27/0203 ,  H01L27/0629 ,  H01L27/0682

摘要： A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell.

摘要翻译： 一种配置半导体集成电路（IC）的方法包括将电池区域布置在单元电池的中心。 电容器/电阻器区域沿着单位电池的左边缘部分和右边缘部分布置。 电容器/电阻器区域包括具有相同长度的多个有源电阻器和具有等于多个有源电阻器的长度的宽度的电容器。 此外，第一导电层纵向设置在每个电容器/电阻器区域中，以便接触单电池的左边缘部分和右边缘部分。

公开(公告)号：US20080052482A1

公开(公告)日：2008-02-28

申请号：US11775780

申请日：2007-07-10

申请人： Joo-Sun CHOI ,  Won-Chang JUNG ,  Hi-Choon LEE ,  Sung-Min YIM ,  Chul-Woo PARK ,  Won-Il BAE

发明人： Joo-Sun CHOI ,  Won-Chang JUNG ,  Hi-Choon LEE ,  Sung-Min YIM ,  Chul-Woo PARK ,  Won-Il BAE

IPC分类号： G06F12/00

CPC分类号： G11C7/1045 ,  G11C7/1072

摘要： In an embodiment, a semiconductor memory device includes a clock latency that can be controlled responsive to whether or not an output order of burst data is reordered. The semiconductor memory device may comprise a control unit and a latency control unit. The control unit may generate a latency control signal having a logic level that varies depending on whether or not an output order of burst data is reordered. The latency control unit may control a latency value in response to the latency control signal. The semiconductor memory device and the method of controlling the latency value responsive to a reordering of the burst data allow for an optimally fast memory access time.

摘要翻译： 在一个实施例中，半导体存储器件包括响应于突发数据的输出顺序是否被重新排序而被控制的时钟等待时间。 半导体存储器件可以包括控制单元和等待时间控制单元。 控制单元可以生成具有根据突发数据的输出顺序是否被重新排列而变化的逻辑电平的等待时间控制信号。 延迟控制单元可以响应于等待时间控制信号来控制等待时间值。 半导体存储器件和响应于突发数据的重排序来控制延迟值的方法允许最佳的快速存储器存取时间。

公开(公告)号：US06927488B2

公开(公告)日：2005-08-09

申请号：US10372336

申请日：2003-02-25

申请人： Jei-Hwan Yoo ,  Byung-Chul Kim ,  Won-Il Bae

发明人： Jei-Hwan Yoo ,  Byung-Chul Kim ,  Won-Il Bae

IPC分类号： G11C5/02 ,  G11C16/12 ,  H01L23/34

CPC分类号： G11C16/12

摘要： A semiconductor device package includes a plurality of semiconductor memory devices whose address input terminals are commonly connected to the external address input pins of the package, and an internal address generating device for using an address signal applied through at least one of the address input pins to select one of the memory devices to perform a read/write data operation. Only the selected memory device is enabled to perform the read/write operation on a memory cell corresponding to the received address signal. The external pin configuration of the semiconductor device package is compatible with a conventional memory board layout.

摘要翻译： 半导体器件封装包括多个半导体存储器件，其地址输入端子共同连接到封装的外部地址输入引脚，以及内部地址产生器件，用于使用通过至少一个地址输入引脚施加的地址信号 选择一个存储器件来执行读/写数据操作。 只有选择的存储器件被使能以对与所接收的地址信号相对应的存储单元执行读/写操作。 半导体器件封装的外部引脚配置与传统的存储器板布局兼容。

公开(公告)号：US06310813B1

公开(公告)日：2001-10-30

申请号：US09358610

申请日：1999-07-21

申请人： Won-Il Bae

发明人： Won-Il Bae

IPC分类号： G11C700

CPC分类号： G11C11/406

摘要： Refreshing of a portion of a DRAM device is bypassed when carrying out a refreshing operation on the DRAM device. By bypassing the refreshing of a portion of the DRAM device when carrying out a refreshing operation, the operational speed of the DRAM device and of systems that use the DRAM device can be increased, and/or the power consumption thereof can be decreased. More specifically, graphic memory apparatus include a DRAM device that is divided into a frame buffer zone that supplies pixel data for a display and at least one other zone, such as a z buffer and/or a texture storing zone. Refreshing of the frame buffer zone is bypassed when carrying out a refreshing operation on the DRAM device. In a preferred embodiment, indications of a starting DRAM address and an ending DRAM address for the frame buffer may be stored. A refreshing operation is performed only on those DRAM addresses that fall outside the starting address and the ending address.

摘要翻译： 当在DRAM设备上执行刷新操作时，旁路DRAM设备的一部分的刷新。 通过在执行刷新操作时绕过DRAM设备的一部分的刷新，可以增加DRAM设备和使用DRAM设备的系统的操作速度，和/或可以降低其功耗。 更具体地，图形存储装置包括被分成提供用于显示的像素数据的帧缓冲器区域和诸如z缓冲器和/或纹理存储区域的至少一个其他区域的DRAM设备。 在DRAM设备上执行刷新操作时，旁路帧缓冲区的刷新。 在优选实施例中，可以存储用于帧缓冲器的起始DRAM地址和结束DRAM地址的指示。 仅在落在起始地址和结束地址之外的那些DRAM地址上执行刷新操作。

公开(公告)号：US20050073033A1

公开(公告)日：2005-04-07

申请号：US10372336

申请日：2003-02-25

申请人： Jei-Hwan Yoo ,  Byung-Chul Kim ,  Won-Il Bae

发明人： Jei-Hwan Yoo ,  Byung-Chul Kim ,  Won-Il Bae

IPC分类号： G11C5/02 ,  G11C16/12 ,  H01L23/02 ,  H01L23/34

CPC分类号： G11C16/12

摘要： A semiconductor device package includes a plurality of semiconductor memory devices whose address input terminals are commonly connected to the external address input pins of the package, and an internal address generating device for using an address signal applied through at least one of the address input pins to select one of the memory devices to perform a read/write data operation. Only the selected memory device is enabled to perform the read/write operation on a memory cell corresponding to the received address signal. The external pin configuration of the semiconductor device package is compatible with a conventional memory board layout.

公开(公告)号：US06529432B2

公开(公告)日：2003-03-04

申请号：US10144517

申请日：2002-05-13

申请人： Byung-Chul Kim ,  Won-Il Bae

发明人： Byung-Chul Kim ,  Won-Il Bae

IPC分类号： G11C700

CPC分类号： G11C7/065

摘要： A semiconductor memory device includes a memory cell array and a differential amplifying and latching circuit for latching and outputting each of signal pairs output from the memory cell array in case of a first latency operation, and for amplifying a voltage difference of each of the signal pairs output from the memory cell array in case of a second latency operation.

公开(公告)号：US20070025164A1

公开(公告)日：2007-02-01

申请号：US11453518

申请日：2006-06-15

申请人： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

发明人： Jun-Hyung Kim ,  Won-Il Bae ,  Seong-Jin Jang

IPC分类号： G11C7/00

CPC分类号： G11C5/145

摘要： A voltage generating circuit for a semiconductor memory device. The voltage generating circuit includes a multi-boosting unit for stepping up a power supply voltage, a transfer transistor connected to a final boosting node of the multi-boosting unit and an output node, and a charge-sharing element, electrically connected to the final boosting node and a gate node of the transfer transistor, enabled during at least a part of the period the power supply voltage is stepped-up by the multi-boosting unit and performing charge sharing between the final boosting node and the gate node of the transfer transistor.

摘要翻译： 一种用于半导体存储器件的电压产生电路。 电压产生电路包括用于升高电源电压的多升压单元，连接到多升压单元的最终升压节点的输出晶体管和输出节点，以及与最终的电连接电连接的电荷共享元件 所述传输晶体管的升压节点和栅极节点在所述周期的至少一部分期间被使能，所述多个升压单元对所述电源电压进行升压，并且在所述最终升压节点和所述转移的所述栅极节点之间执行电荷共享 晶体管。

公开(公告)号：US06201745B1

公开(公告)日：2001-03-13

申请号：US09544358

申请日：2000-04-06

申请人： Hoon Ryu ,  Won-Il Bae

发明人： Hoon Ryu ,  Won-Il Bae

IPC分类号： G11C2900

CPC分类号： G11C29/842

摘要： A semiconductor memory device has a sub word line driver structure and includes a main word line decoder driver, an address programming circuit, and a redundant main word line decoder driver. When row address bit signals are input, the main word line decoder driver drives a main word line corresponding to the row address bit signals regardless of a row replacement with redundant rows. If the row address bit signals correspond to programmed defective row address bit signals, the address programming circuit generates a redundant row select signal, in response to which the activated main word line is deactivated and a redundant main word line is activated. According to the redundant row replacement scheme of the present invention, access time is reduced without an increase of a layout area.

摘要翻译： 半导体存储器件具有副字线驱动器结构，并且包括主字线解码器驱动器，地址编程电路和冗余主字线解码器驱动器。 当行地址位信号被输入时，主字线解码器驱动器驱动对应于行地址位信号的主字线，而不管具有冗余行的行替换。 如果行地址位信号对应于编程的缺陷行地址位信号，则地址编程电路产生冗余行选择信号，响应于激活的主字线被激活并且冗余主字线被激活。 根据本发明的冗余行替换方案，在不增加布局区域的情况下，可以减少访问时间。

公开(公告)号：US08307318B2

公开(公告)日：2012-11-06

申请号：US12585133

申请日：2009-09-04

申请人： Sung-hoon Kim ,  Won-Il Bae

发明人： Sung-hoon Kim ,  Won-Il Bae

IPC分类号： G06F17/50 ,  G06F19/00 ,  H01L25/00 ,  H03K19/00

CPC分类号： H01L27/0203 ,  H01L27/0629 ,  H01L27/0682

摘要： A method of configuring a semiconductor integrated circuit (IC) includes arranging a circuit region in the center of a unit cell. Capacitor/resistor regions are arranged along the left and right edge portions of the unit cell. The capacitor/resistor regions include a plurality of active resistors having the same length and a capacitor having a width equal to the length of the plurality of active resistors. In addition, a first conductive layer is arranged longitudinally in each of the capacitor/resistor regions so as to contact the left and right edge portions of the unit cell.

摘要翻译： 一种配置半导体集成电路（IC）的方法包括将电池区域布置在单元电池的中心。 电容器/电阻器区域沿着单位电池的左边缘部分和右边缘部分布置。 电容器/电阻器区域包括具有相同长度的多个有源电阻器和具有等于多个有源电阻器的长度的宽度的电容器。 此外，第一导电层纵向设置在每个电容器/电阻器区域中，以便接触单电池的左边缘部分和右边缘部分。