公开(公告)号：US20150008452A1

公开(公告)日：2015-01-08

申请号：US14492628

申请日：2014-09-22

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L29/78 ,  H01L29/16 ,  H01L29/165

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

摘要翻译： 半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。 沟道区位于衬底上并位于第一和第二应力产生外延区之间。 栅电极在沟道区上。 沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

公开(公告)号：US20120112156A1

公开(公告)日：2012-05-10

申请号：US13220777

申请日：2011-08-30

申请人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

发明人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

IPC分类号： H01L45/00

CPC分类号： H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

摘要翻译： 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。

公开(公告)号：US08853010B2

公开(公告)日：2014-10-07

申请号：US13368584

申请日：2012-02-08

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L21/00 ,  H01L21/84 ,  H01L21/336 ,  H01L21/337 ,  H01L21/338 ,  H01L21/339 ,  H01L29/165 ,  H01L29/78 ,  H01L29/66 ,  H01L21/8238

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.

摘要翻译： 半导体器件包括衬底和在衬底上彼此间隔开的第一和第二应力产生外延区域。 沟道区位于衬底上并位于第一和第二应力产生外延区之间。 栅电极在沟道区上。 沟道区域是外延层，并且第一和第二应力产生外延区域对沟道区域施加应力。

公开(公告)号：US08664633B2

公开(公告)日：2014-03-04

申请号：US13220777

申请日：2011-08-30

申请人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

发明人： Heung-Kyu Park ,  In-Sun Park ,  In-Gyu Baek ,  Byeong-Chan Lee ,  Sang-Bom Kang ,  Woo-Bin Song

IPC分类号： H01L29/06

CPC分类号： H01L27/1021 ,  G11C13/0002 ,  G11C2213/71 ,  H01L27/101 ,  H01L27/2409 ,  H01L27/249 ,  H01L45/04 ,  H01L45/1226 ,  H01L45/146

摘要： A non-volatile memory device may include a first wordline on a substrate, an insulating layer on the first wordline, and a second wordline on the insulating layer so that the insulating layer is between the first and second wordlines. A bit pillar may extend adjacent the first wordline, the insulating layer, and the second wordline in a direction perpendicular with respect to a surface of the substrate, and the bit pillar may be electrically conductive. In addition, a first memory cell may include a first resistance changeable element electrically coupled between the first wordline and the bit pillar, and a second memory cell may include a second resistance changeable element electrically coupled between the second wordline and the bit pillar. Related methods and systems are also discussed.

摘要翻译： 非易失性存储器件可以包括衬底上的第一字线，第一字线上的绝缘层和绝缘层上的第二字线，使得绝缘层在第一和第二字线之间。 位柱可以在相对于衬底的表面垂直的方向上相邻于第一字线，绝缘层和第二字线延伸，并且位柱可以是导电的。 此外，第一存储单元可以包括电耦合在第一字线和位柱之间的第一电阻可变元件，并且第二存储单元可以包括电耦合在第二字线和位柱之间的第二电阻可变元件。 还讨论了相关方法和系统。

公开(公告)号：US09595611B2

公开(公告)日：2017-03-14

申请号：US14262712

申请日：2014-04-26

申请人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

发明人： Seok-Hoon Kim ,  Bon-Young Koo ,  Nam-Kyu Kim ,  Woo-Bin Song ,  Byeong-Chan Lee ,  Su-Jin Jung

IPC分类号： H01L29/78 ,  H01L21/8234 ,  H01L29/66 ,  H01L27/12

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

摘要： A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

摘要翻译： 半导体器件可以包括在衬底上并排形成的第一和第二鳍片，形成在第一鳍片上并具有杂质的第一掺杂浓度的第一升高掺杂区域，形成在第二鳍片上的第二高掺杂区域， 将第一升高掺杂区域和第二升高掺杂区域彼此连接的桥。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20150035023A1

公开(公告)日：2015-02-05

申请号：US14262712

申请日：2014-04-26

申请人： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

发明人： Seok-Hoon KIM ,  Bon-Young KOO ,  Nam-Kyu KIM ,  Woo-Bin SONG ,  Byeong-Chan LEE ,  Su-Jin JUNG

IPC分类号： H01L29/78

CPC分类号： H01L29/785 ,  H01L21/823431 ,  H01L27/0886 ,  H01L27/1211 ,  H01L29/0847 ,  H01L29/66545 ,  H01L29/66795 ,  H01L29/6681

摘要： A semiconductor device may include first and second fins formed side by side on a substrate, a first elevated doped region formed on the first fin and having a first doping concentration of impurities, a second elevated doped region formed on the second fin, and a first bridge connecting the first elevated doped region and the second elevated doped region to each other. Methods of manufacturing such a semiconductor device are also disclosed.

摘要翻译： 半导体器件可以包括在衬底上并排形成的第一和第二鳍片，形成在第一鳍片上并具有杂质的第一掺杂浓度的第一升高掺杂区域，形成在第二鳍片上的第二高掺杂区域， 将第一升高掺杂区域和第二升高掺杂区域彼此连接的桥。 还公开了制造这种半导体器件的方法。

公开(公告)号：US20130005096A1

公开(公告)日：2013-01-03

申请号：US13368584

申请日：2012-02-08

申请人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

发明人： Heung-Kyu Park ,  Woo-Bin Song ,  Nam-Kyu Kim ,  Su-Jin Jung ,  Byeong-Chan Lee ,  Young-Pil Kim ,  Sun-Ghil Lee

IPC分类号： H01L21/8238 ,  H01L21/336

CPC分类号： H01L29/7848 ,  H01L21/823807 ,  H01L21/823814 ,  H01L29/1608 ,  H01L29/165 ,  H01L29/66545 ,  H01L29/66621 ,  H01L29/66651 ,  H01L29/78

摘要： A semiconductor device comprises a substrate and first and second stress-generating epitaxial regions on the substrate and spaced apart from each other. A channel region is on the substrate and positioned between the first and second stress-generating epitaxial regions. A gate electrode is on the channel region. The channel region is an epitaxial layer, and the first and second stress-generating epitaxial regions impart a stress on the channel region.