公开(公告)号：US08198627B2

公开(公告)日：2012-06-12

申请号：US12906266

申请日：2010-10-18

申请人： Woo-seop Jeong

发明人： Woo-seop Jeong

IPC分类号： H01L23/58

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G11C29/48 ,  H01L22/32 ,  H01L2224/05554 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

摘要翻译： 半导体器件包括至少一种第一类型的焊盘和至少一种第二类型的焊盘，其具有与第一类型焊盘不同的区域。 焊盘连接单元在测试模式期间将所述至少一个第二类型的焊盘电耦合到所述半导体器件的集成电路，并且在正常操作模式期间将所述至少一个第二类型的焊盘与所述集成电路断开。

公开(公告)号：US20120106283A1

公开(公告)日：2012-05-03

申请号：US13237353

申请日：2011-09-20

申请人： Hui-Kap Yang ,  Woo-Seop Jeong ,  Chul-Sung Park

发明人： Hui-Kap Yang ,  Woo-Seop Jeong ,  Chul-Sung Park

IPC分类号： G11C11/402 ,  G11C8/00 ,  G11C8/04

CPC分类号： G11C29/20 ,  G11C2029/1802

摘要： A row address control circuit of a semiconductor memory device including dynamic memory cells includes a test mode setting unit, an address counter and a row address generating unit. The test mode setting unit is configured to provide a test mode signal that indicates whether a test operation is performed or not, in response to a test command; the address counter is configured to generate a first address that increases gradually; and the row address generating unit is configured to selectively choose one of the first address and a second address as a refresh address based on the test mode signal, the second address being externally provided.

摘要翻译： 包括动态存储单元的半导体存储器件的行地址控制电路包括测试模式设置单元，地址计数器和行地址生成单元。 测试模式设置单元被配置为响应于测试命令提供指示是否执行测试操作的测试模式信号; 地址计数器被配置为生成逐渐增加的第一地址; 并且行地址生成单元被配置为基于测试模式信号选择性地选择第一地址和第二地址中的一个作为刷新地址，第二地址被外部提供。

公开(公告)号：US20080157076A1

公开(公告)日：2008-07-03

申请号：US12004401

申请日：2007-12-20

申请人： Woo-Seop Jeong

发明人： Woo-Seop Jeong

IPC分类号： H01L23/58

CPC分类号： G11C29/1201 ,  G01R31/2884 ,  G11C29/48 ,  H01L22/32 ,  H01L2224/05554 ,  H01L2924/13091 ,  H01L2924/3011 ,  H01L2924/00

摘要： A semiconductor device includes at least one first type of pad and at least one second type of pad having a different area from the first type of pad. A pad connection unit electrically couples the at least one second type of pad to an integrated circuit of the semiconductor device during a test mode, and disconnects the at least one second type of pad from the integrated circuit during a normal operating mode.

摘要翻译： 半导体器件包括至少一种第一类型的焊盘和至少一种第二类型的焊盘，其具有与第一类型焊盘不同的区域。 焊盘连接单元在测试模式期间将所述至少一个第二类型的焊盘电耦合到所述半导体器件的集成电路，并且在正常操作模式期间将所述至少一个第二类型的焊盘与所述集成电路断开。

公开(公告)号：US07336558B2

公开(公告)日：2008-02-26

申请号：US11264512

申请日：2005-10-31

申请人： Woo-Seop Jeong

发明人： Woo-Seop Jeong

IPC分类号： G11C8/00

CPC分类号： G11C29/1201 ,  G11C5/066 ,  G11C29/48

摘要： A semiconductor memory device is provided which comprises a group of address pads and an input circuit configured to receive a first address from the address pads at a first transition of an external clock signal and a second address from the address pads at a second transition of the external clock signal.

摘要翻译： 提供了一种半导体存储器件，其包括一组地址焊盘和一个输入电路，该输入电路被配置为在外部时钟信号的第一转变处接收来自地址焊盘的第一地址，并且在第二转换时从地址焊盘接收第二地址 外部时钟信号。

公开(公告)号：US07168017B2

公开(公告)日：2007-01-23

申请号：US10648086

申请日：2003-08-26

申请人： Sung-ryul Kim ,  Jong-bok Tcho ,  Woo-seop Jeong

发明人： Sung-ryul Kim ,  Jong-bok Tcho ,  Woo-seop Jeong

IPC分类号： G11C29/00

CPC分类号： G11C29/1201 ,  G11C7/1066 ,  G11C11/401 ,  G11C29/48

摘要： A memory device, such as a DDR SDRAM, may be provided in which subsets of data output circuits of the device can be selectively enabled to allow sets of data output pins to be connected in common in a testing configuration. In some embodiments, a memory device includes a plurality of data output circuits, respective ones of which are configured to receive data from respective internal data lines and respective ones of which are coupled to respective data input/output pins. The device further includes a data output control circuit operative to selectively enable subsets of the plurality of data output circuits to drive their respective corresponding data input/output pins responsive to an externally-applied control signal. The data output control circuit may be operative to selectively cause subsets of the plurality of data output circuits to present a high impedance at their respective corresponding data input/output pins. The invention may be embodied as devices and methods.

摘要翻译： 可以提供诸如DDR SDRAM的存储器件，其中可以选择性地启用器件的数据输出电路的子集，以允许在测试配置中将数据输出引脚的组合相互连接。 在一些实施例中，存储器装置包括多个数据输出电路，其中各个数据输出电路被配置为从相应的内部数据线接收数据，并且其中相应的数据输出电路被耦合到相应的数据输入/输出引脚。 该装置还包括数据输出控制电路，其可操作以响应于外部施加的控制信号选择性地使多个数据输出电路的子集驱动其相应的数据输入/输出引脚。 数据输出控制电路可以有效地选择性地使多个数据输出电路的子集在各自相应的数据输入/输出引脚上呈现高阻抗。 本发明可以体现为设备和方法。

公开(公告)号：US07042800B2

公开(公告)日：2006-05-09

申请号：US10951881

申请日：2004-09-29

申请人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

发明人： Young-gu Kang ,  Jong-hyun Choi ,  Woo-seop Jeong ,  Ki-ho Jang ,  Jung-yong Choi

IPC分类号： G11C8/00

CPC分类号： G11C7/1045 ,  G11C29/46

摘要： A memory system, memory device, and method for setting an operating mode of a memory device include a memory cell array; row and column decoders which select a row and a column of the memory cell array, respectively, according to a multi-bit address signal; and a mode control circuit which receives at least one bit from the multi-bit address signal used in the selection of the row or the column, and which sets an operating mode of the memory device according to the at least one bit, wherein the operating mode is one of a burst length mode, a DLL reset mode, a test mode, a CAS latency mode, and a burst type mode.

摘要翻译： 用于设置存储器件的操作模式的存储器系统，存储器件和方法包括存储器单元阵列; 行和列解码器，其分别根据多位地址信号选择存储单元阵列的行和列; 以及模式控制电路，其从在行或列的选择中使用的多位地址信号接收至少一个位，并且根据至少一个位设置存储器件的操作模式，其中操作 模式是突发长度模式，DLL复位模式，测试模式，CAS延迟模式和突发类型模式之一。

公开(公告)号：US20050071582A1

公开(公告)日：2005-03-31

申请号：US10732868

申请日：2003-12-10

申请人： Han-Gu Sohn ,  Hai-Jeong Sohn ,  Sei-Jin Kim ,  Woo-seop Jeong

发明人： Han-Gu Sohn ,  Hai-Jeong Sohn ,  Sei-Jin Kim ,  Woo-seop Jeong

IPC分类号： G11C11/407 ,  G06F12/00 ,  G06F12/04 ,  G06F13/00 ,  G11C7/10

CPC分类号： G11C7/1057 ,  G06F12/04 ,  G11C7/10 ,  G11C7/1051 ,  G11C7/1078 ,  G11C7/1084

摘要： Circuits and methods for controlling data I/O operations in semiconductor memory devices to provide variable data I/O widths for read, write and active memory operations. Circuits and methods for selectively controlling a data width of a data I/O buffer “on the fly” to enable variable data I/O widths during memory access operations.

摘要翻译： 用于控制半导体存储器件中数据I / O操作的电路和方法，为读，写和有效存储器操作提供可变数据I / O宽度。 用于选择性地控制数据I / O缓冲器的数据宽度的电路和方法，以便在存储器访问操作期间实现可变数据I / O宽度。

公开(公告)号：US06476646B2

公开(公告)日：2002-11-05

申请号：US09956577

申请日：2001-09-18

申请人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

发明人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

IPC分类号： G01R1900

CPC分类号： H03F3/347 ,  G11C7/062 ,  G11C7/065 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/45418 ,  H03F2203/45562 ,  H03F2203/45571 ,  H03F2203/45574 ,  H03F2203/45644 ,  H03F2203/45652 ,  H03F2203/45674 ,  H03K5/2481

摘要： A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and a complement of the input signal. The sense amplifier includes cross-coupled transistors. Each unique cross-coupled transistor is coupled to a corresponding unique transistor formed as a diode. A resistor is coupled in series between one cross-coupled resistor and an input port receiving the input signal, and another resistor is coupled in series between the other cross-coupled transistor and another input port receiving the complement of the input signal. Resistances associated with the sources of each cross-coupled transistor provide the resistance of the resistors.

摘要翻译： 半导体集成电路包括用于放大输入信号的读出放大器和输入信号的补码。 读出放大器包括交叉耦合晶体管。 每个独特的交叉耦合晶体管耦合到形成为二极管的对应的唯一晶体管。 电阻器串联耦合在一个交叉耦合电阻器和接收输入信号的输入端口之间，另一个电阻器串联耦合在另一个交叉耦合晶体管和另一个输入端口，该输入端口接收输入信号的补码。 与每个交叉耦合晶体管的源极相关的电阻提供了电阻器的电阻。

公开(公告)号：US06326815B1

公开(公告)日：2001-12-04

申请号：US09547987

申请日：2000-04-12

申请人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

发明人： Jae-yoon Sim ,  Hyun-soon Jang ,  Woo-seop Jeong ,  Kyung-ho Kim

IPC分类号： G01R1900

CPC分类号： H03F3/347 ,  G11C7/062 ,  G11C7/065 ,  H03F3/45183 ,  H03F3/4565 ,  H03F3/72 ,  H03F2203/45418 ,  H03F2203/45562 ,  H03F2203/45571 ,  H03F2203/45574 ,  H03F2203/45644 ,  H03F2203/45652 ,  H03F2203/45674 ,  H03K5/2481

摘要： A semiconductor integrated circuit includes a sense amplifier for amplifying an input signal and an complementary input signal, a full differential amplifier for amplifying the output of the sense amplifier, and a latch for latching the output of the full differential amplifier and outputting the latched output. The full differential amplifier includes a first differential amplifying unit for increasing the voltage of an output port when the level of an input signal input through an input port is larger than the level of an complementary input signal input through an complementary input port and reducing the voltage of the output port when the level of the input signal is lower than the level of the complementary input signal, a second differential amplifying unit for reducing the voltage of an complementary output port when the level of the input signal is larger than the level of the complementary input signal and increasing the voltage of the complementary output port when the level of the input signal is lower than the level of the complementary input signal, and an output voltage level control circuit connected between the output port and the complementary output port. The output voltage level control circuit controls the voltage levels of the output signals output from the output port and the complementary output port. The sense amplifier can stabilize the operation of the latch by reducing the mean voltage level of the output signal even when the supply A voltage increases, can easily control the voltage gain of the full differential amplifier by controlling the resistance, and stably operates at high speed. The current sense amplifier can include resistors associated with PMOS transistors to avoid unstable operation caused by increased transconductance arising from higher operating voltage.

摘要翻译： 半导体集成电路包括用于放大输入信号和互补输入信号的读出放大器，用于放大读出放大器的输出的全差分放大器和用于锁存全差分放大器的输出并输出锁存输出的锁存器。 全差分放大器包括第一差分放大单元，用于当通过输入端口输入的输入信号的电平大于通过互补输入端口输入的互补输入信号的电平时，增加输出端口的电压，并降低电压 当所述输入信号的电平低于所述互补输入信号的电平时，所述第二差分放大单元用于当所述输入信号的电平大于所述输入信号的电平时降低互补输出端口的电压; 互补输入信号，并且当输入信号的电平低于互补输入信号的电平时增加互补输出端口的电压，以及连接在输出端口和互补输出端口之间的输出电压电平控制电路。 输出电压电平控制电路控制从输出端口和互补输出端口输出的输出信号的电压电平。 读出放大器可以通过降低输出信号的平均电压电平来稳定锁存器的操作，即使电源A电压增加，也可以通过控制电阻容易地控制全差分放大器的电压增益，并可以高速稳定运行 。 电流检测放大器可以包括与PMOS晶体管相关联的电阻器，以避免由于较高工作电压引起的跨导增加引起的不稳定操作。

公开(公告)号：US6151270A

公开(公告)日：2000-11-21

申请号：US134586

申请日：1998-08-14

申请人： Woo-Seop Jeong

发明人： Woo-Seop Jeong

IPC分类号： G11C11/407 ,  G11C7/10 ,  G11C7/22 ,  G11C11/401 ,  G11C8/00

CPC分类号： G11C7/1072 ,  G11C7/22

摘要： Integrated circuit memory devices include a column select signal generator which generates a column select signal (CSL) having leading and trailing edges and a preferred timing controller. The timing controller, which is electrically coupled to the column select signal generator and is responsive to at least one latency state signal (e.g., CLy), adjusts the timing of at least one of the leading and trailing edges of the column select signal pulse as a function of the value of the at least one latency state signal. Here, the value of the latency state signal can be adjusted to cause a shift in the timing of the column select signal (CSL) and thereby reduce the likelihood of reading errors. In particular, the timing controller is responsive to a first internal clock signal (e.g., PCLK) and generates first and second control signals as CSLE and CSLD. The column select signal generator is responsive to the first and second control signals. The first control signal is preferably delayed and inverted relative to the first internal clock signal by a first delay and the second control signal is preferably delayed relative to the first internal clock signal by a second delay which is less than the first delay. The timing controller also adjusts the timing of at least one of the leading and trailing edges of the column select signal by adjusting the values of the first and second delays as a function of the value of the at least one latency state signal.

摘要翻译： 集成电路存储器件包括产生具有前沿和后沿的列选择信号（CSL）的列选择信号发生器和优选的时序控制器。 电气耦合到列选择信号发生器并且响应于至少一个等待时间状态信号（例如，CLy）的定时控制器将列选择信号脉冲的前沿和后沿中的至少一个的定时调整为 是至少一个等待时间状态信号的值的函数。 这里，等待状态信号的值可以被调整以引起列选择信号（CSL）的定时偏移，从而降低读取错误的可能性。 特别地，定时控制器响应于第一内部时钟信号（例如，PCLK），并且产生第一和第二控制信号为+ E，ovs CSLE + EE和CSLD。 列选择信号发生器响应于第一和第二控制信号。 优选地，第一控制信号相对于第一内部时钟信号延迟和反相第一延迟，并且第二控制信号优选地相对于第一内部时钟信号延迟小于第一延迟的第二延迟。 定时控制器还通过调整第一和第二延迟的值作为至少一个等待时间状态信号的值的函数来调整列选择信号的前沿和后沿中的至少一个的定时。