公开(公告)号：US20100200904A1

公开(公告)日：2010-08-12

申请号：US12368023

申请日：2009-02-09

Applicant: YouSeok SUH ,  Sung-Yong CHUNG ,  Ya-Fen LIN ,  Yi-Ching WU

Inventor： YouSeok SUH ,  Sung-Yong CHUNG ,  Ya-Fen LIN ,  Yi-Ching WU

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L27/11524 ,  H01L21/28282 ,  H01L27/11521 ,  H01L27/11568 ,  H01L27/1157 ,  H01L29/4234 ,  H01L29/66825 ,  H01L29/66833 ,  H01L29/7881 ,  H01L29/792

Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.

Abstract translation: 公开了基于栅极边缘效应形成半导体通道的方法和结构。 在一个实施例中，NAND闪存器件包括存储器晶体管的多个NAND串。 每个存储晶体管包括形成在电荷俘获层上的电荷俘获层和栅电极。 基于与相邻的一对存储晶体管相关的栅极边缘效应，存储晶体管彼此靠近形成在相邻的一对存储晶体管之间形成沟道。

公开(公告)号：US07723774B2

公开(公告)日：2010-05-25

申请号：US11775851

申请日：2007-07-10

Applicant: Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

Inventor： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC: H01L29/788

CPC classification number: G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

Abstract: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Abstract translation: 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US20060166661A1

公开(公告)日：2006-07-27

申请号：US11041965

申请日：2005-01-26

Applicant: Ya-Fen Lin

Inventor： Ya-Fen Lin

IPC: H04M3/00

CPC classification number: H04M1/67 ,  H04M1/677

Abstract: A wireless communication device having a number-limited back calling function is disclosed, comprising a receiving module receiving a telephone number corresponding to an in-coming call, a memory storing at least a limited telephone number, a comparison module comparing if the telephone number of the in-coming call is the same as the limited telephone number stored in the memory, a limiting module limiting a back call from being sent to a communication device corresponding to the in-coming call with the limited telephone number if the comparison result is true, and a back calling interface calling back to the telephone number corresponding to the in-coming call if the comparison result is different.

Abstract translation: 公开了一种具有数量有限的返回呼叫功能的无线通信装置，包括：接收模块，其接收与进入呼叫相对应的电话号码;至少存储有限电话号码的存储器;比较模块， 来电呼叫与存储在存储器中的有限电话号码相同，如果比较结果为真，则限制模块将拒绝呼叫限制为与具有有限电话号码的呼入呼叫相对应的通信设备 如果比较结果不同，则返回呼叫接口回呼对应于来电呼叫的电话号码。

公开(公告)号：US08164135B2

公开(公告)日：2012-04-24

申请号：US12773811

申请日：2010-05-04

Applicant: Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

Inventor： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC: H01L29/788

CPC classification number: G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

Abstract: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Abstract translation: 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US07848146B2

公开(公告)日：2010-12-07

申请号：US12407228

申请日：2009-03-19

Applicant: Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

Inventor： Youseok Suh ,  Ya-Fen Lin ,  Coling Stewart Bill ,  Takao Akaogi ,  Yi-Ching Wu

IPC: G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483

Abstract: A method for partial local self-boosting of a memory cell channel is disclosed. As a part of memory cell channel partial local self-boosting, an isolating memory cell located on a source side of a program inhibited memory cell is turned off and a gating memory cell located on a drain side of the program inhibited memory cell is used to pass a pre-charge voltage to the program inhibited memory cell to provide a pre-charge voltage to a channel of the program inhibited memory cell. Moreover, a pre-charge voltage is passed to a buffering memory cell located on the source side of the program inhibited memory cell to provide a pre-charge voltage to a channel of the buffering memory cell and the gating memory cell that is located on the drain side of the program inhibited memory cell is turned off. During programming, a program voltage is applied to the gate of the program inhibited memory cell where a channel voltage of the program inhibited memory cell is raised above a level raised by the pre-charge voltage.

Abstract translation: 公开了一种用于存储器单元通道的局部局部自升压的方法。 作为存储单元通道部分局部自升压的一部分，位于程序禁止存储单元的源极侧的隔离存储单元被截止，并且位于程序禁止存储单元的漏极侧的门控存储单元被用于 将预充电电压传递到程序禁止的存储单元，以向编程禁止的存储单元的通道提供预充电电压。 此外，预充电电压被传递到位于程序禁止的存储单元的源极侧的缓冲存储单元，以向缓冲存储单元的通道和位于该存储单元上的选通存储单元提供预充电电压 程序的漏极侧禁止存储单元关闭。 在编程期间，将程序禁止存储单元的通道电压升高到由预充电电压升高的电平以上的程序禁止存储单元的栅极上施加编程电压。

公开(公告)号：US07790518B2

公开(公告)日：2010-09-07

申请号：US12027916

申请日：2008-02-07

Applicant: Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

Inventor： Bomy Chen ,  Ya-Fen Lin ,  Zhitang Song ,  Songlin Feng

IPC: H01L21/82

CPC classification number: H01L28/20 ,  H01C17/267 ,  H01L22/22

Abstract: A method of trimming down the volume of a semiconductor resistor element using electrical resistance feedback. After forming conductive material disposed between a pair of electrodes, a voltage is applied to the electrodes to produce an electrical current through the conductive material sufficient to heat and melt away a portion of the conductive material. By reducing the volume of the conductive material, its resistance is increased. The application of the voltage is ceased once the desired dimensions (and thus resistivity) of the conductive material is reached. The resulting semiconductor resistor element could have a fixed resistance, or could have a variable resistance (by using phase change memory material).

Abstract translation: 使用电阻反馈来减少半导体电阻元件的体积的方法。 在形成设置在一对电极之间的导电材料之后，向电极施加电压以产生通过导电材料的电流，足以加热和熔化掉导电材料的一部分。 通过减小导电材料的体积，其电阻增加。 一旦达到导电材料的所需尺寸（因此电阻率），电压的施加就会停止。 所得到的半导体电阻元件可以具有固定电阻，或者可以具有可变电阻（通过使用相变存储器材料）。

公开(公告)号：US07544569B2

公开(公告)日：2009-06-09

申请号：US11516431

申请日：2006-09-05

Applicant: Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

Inventor： Feng Gao ,  Ya-Fen Lin ,  John W. Cooksey ,  Changyuan Chen ,  Yuniarto Widjaja ,  Dana Lee

IPC: H01L21/336

CPC classification number: H01L29/42336 ,  G11C16/0425 ,  G11C16/0483 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11556 ,  H01L29/42328

Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type and a second region of the second conductivity type in the substrate, spaced apart from the first region, thereby defining a channel region therebetween. A plurality of floating gates are spaced apart from one another and each is insulated from the channel region. A plurality of control gates are spaced apart from one another, with each control gate insulated from the channel region. Each of the control gate is between a pair of floating gates and is capacitively coupled to the pair of floating gates. A plurality of select gates are spaced apart from one another, with each select gate insulated from the channel region. Each select gate is between a pair of floating gates.

Abstract translation: 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括第二导电类型的第一区域和第二导电类型的第二区域，与第一区域间隔开，由此在其间限定沟道区域。 多个浮动栅极彼此间隔开并且各自与沟道区域绝缘。 多个控制栅极彼此间隔开，每个控制栅极与沟道区域绝缘。 每个控制栅极位于一对浮动栅极之间，并且电容耦合到该对浮置栅极。 多个选择栅极彼此间隔开，每个选择栅极与沟道区域绝缘。 每个选择门位于一对浮动门之间。

公开(公告)号：US20090016113A1

公开(公告)日：2009-01-15

申请号：US11775851

申请日：2007-07-10

Applicant: Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

Inventor： Changyuan Chen ,  Ya-Fen Lin ,  Dana Lee

IPC: G11C16/06 ,  H01L29/788 ,  G11C16/16

CPC classification number: G11C16/0458 ,  G11C16/10 ,  H01L27/115 ,  H01L27/11521 ,  H01L29/42328 ,  H01L29/42336 ,  H01L29/7887

Abstract: Nonvolatile flash memory systems and methods are disclosed having a semiconductor substrate of a first conductivity type, including non-diffused channel regions through which electron flow is induced by application of voltage to associated gate elements. A plurality of floating gates are spaced apart from one another and each insulated from the channel region. A plurality of control gates are spaced apart from one another and insulated from the channel region, with each control gate being located between a first floating gate and a second floating gate and capacitively coupled thereto to form a subcell. A plurality of spaced-apart assist gates are insulated from the channel region, with each assist gate being located between and insulated from adjacent subcells. The channel is formed of three regions, two beneath adjacent control gate elements as well as a third region between the first two and beneath an associated assist gate.

Abstract translation: 公开了非挥发性闪速存储器系统和方法，其具有第一导电类型的半导体衬底，包括非扩散沟道区，通过向相关联的栅极元件施加电压而引起电子流。 多个浮动栅极彼此间隔开并且与沟道区域绝缘。 多个控制栅极彼此间隔开并且与沟道区域绝缘，每个控制栅极位于第一浮动栅极和第二浮动栅极之间，并电容耦合到其上以形成子电池。 多个间隔开的辅助栅极与沟道区域绝缘，每个辅助栅极位于相邻子电池之间并且与相邻的子电池绝缘。 通道由三个区域组成，两个位于相邻的控制栅极元件下方，以及位于相关联的辅助栅极之间的第一个两个和第二区域之间。

公开(公告)号：US20070237005A1

公开(公告)日：2007-10-11

申请号：US11810714

申请日：2007-06-06

Applicant: Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

Inventor： Yuniarto Widjaja ,  John Cooksey ,  Changyuan Chen ,  Feng Gao ,  Ya-Fen Lin ,  Dana Lee

IPC: G11C11/34

CPC classification number: G11C16/0425 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/26 ,  G11C16/3431 ,  G11C2216/18 ,  H01L21/28273 ,  H01L27/115 ,  H01L27/11517 ,  H01L27/11521 ,  H01L27/11524 ,  H01L27/11529 ,  H01L29/42328 ,  H01L29/66825 ,  H01L29/7887

Abstract: A split gate NAND flash memory structure is formed on a semiconductor substrate of a first conductivity type. The NAND structure comprises a first region of a second conductivity type in the substrate with a second region of the second conductivity type in the substrate, spaced apart from the first region. A continuous first channel region is defined between the first region and the second region. A plurality of floating gates are spaced apart from one another with each positioned over a separate portion of the channel region. A plurality of control gates are provided with each associated with and adjacent to a floating gate. Each control gate has two portions: a first portion over a portion of the channel region and a second portion over the associated floating gate and capacitively coupled thereto.

Abstract translation: 在第一导电类型的半导体衬底上形成分离栅极NAND闪速存储器结构。 NAND结构包括在衬底中具有第二导电类型的第二区域的第二导电类型的第一区域，与第一区域间隔开。 在第一区域和第二区域之间限定连续的第一通道区域。 多个浮动栅极彼此间隔开，每个浮置栅极位于沟道区域的独立部分上。 设置有多个控制栅极，每个与浮动栅极相关联并与其相邻。 每个控制栅极具有两个部分：沟道区域的一部分上的第一部分和相关联的浮动栅极上的第二部分，并与其电容耦合。

公开(公告)号：US20070076489A1

公开(公告)日：2007-04-05

申请号：US11241582

申请日：2005-09-30

Applicant: Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

Inventor： Ya-Fen Lin ,  Elbert Lin ,  Hieu Tran ,  Jack Frayer ,  Bomy Chen

IPC: G11C11/34

CPC classification number: G11C8/08 ,  G11C16/08

Abstract: A first embodiment of a word line voltage boosting circuit for use with an array of non-volatile memory cells has a capacitor, having two ends, connected to the word line. One end of the capacitor is electrically connected to the word line. The other end of the capacitor is electrically connected to a first voltage source. The word line is also connected through a switch to a second source voltage source. A sequencing circuit activates the switch such that the word line is connected to the second voltage source, and the other end of the capacitor is not connected to the first voltage source. Then the sequencing circuit causes the switch to disconnect the word line from the second voltage source, and connect the second end of the capacitor to the first voltage source. The alternate switching of the connection boosts the voltage on the word line. In a second embodiment, a first word line is electrically connected to a first switch to a first voltage source. An adjacent word line, capacitively coupled to the first word line, is electrically connected to a second switch to a second voltage source. A sequencing circuit activates the first switch and the second switch such that the first word line is connected to the first voltage source, and the second word line is disconnected from the second voltage source. Then the sequencing circuit causes the first switch to disconnect the first word line from the first voltage source, and causes the second word line to be electrically connected to the second voltage source. The alternate switching of the connection boosts the voltage on the first word line, caused by its capacitive coupling to the second word line. A boosted voltage on the word line may be used to improve cycling and yield, where the memory cells of the array are of the floating gate type and erase through the mechanism of Fowler-Nordheim tunneling from the floating gate to a control gate which is connected to the word line.