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    A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET
    2.
    发明申请
    A SEMICONDUCTOR PACKAGE OF A FLIPPED MOSFET 有权
    襟翼MOSFET的半导体封装

    公开(公告)号：US20160104661A9

    公开(公告)日：2016-04-14

    申请号：US13913183

    申请日：2013-06-07

    Applicant: Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

    Inventor： Yan Xun Xue ,  Yueh-Se Ho ,  Hamza Yilmaz ,  Jun Lu

    IPC: H01L23/495

    CPC classification number: H01L23/4951 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49562 ,  H01L24/73 ,  H01L2224/16245 ,  H01L2224/48091 ,  H01L2224/49111 ,  H01L2224/92247 ,  H01L2924/01322 ,  H01L2924/13091 ,  H01L2924/00014 ,  H01L2924/00

    Abstract: The invention relates to a semiconductor package of a flip chip and a method for making the semiconductor package. The semiconductor chip comprises a metal-oxide-semiconductor field effect transistor. On a die paddle including a first base, a second base and a third base, half-etching or punching is performed on the top surfaces of the first base and the second base to obtain plurality of grooves that divide the top surface of the first base into a plurality of areas comprising multiple first connecting areas, and divide the top surface of the second base into a plurality of areas comprising at least a second connecting area. The semiconductor chip is connected to the die paddle at the first connecting areas and the second connecting area.

    Abstract translation: 本发明涉及倒装芯片的半导体封装以及制造半导体封装的方法。 半导体芯片包括金属氧化物半导体场效应晶体管。 在包括第一基底，第二基底和第三基底的裸片上，在第一基底和第二基底的顶表面上进行半蚀刻或冲孔，以获得多个凹槽，该凹槽将第一基底 进入包括多个第一连接区域的多个区域，并且将第二基座的顶表面分成包括至少第二连接区域的多个区域。 半导体芯片在第一连接区域和第二连接区域处连接到管芯焊盘。

    Power semiconductor device and preparation method thereof
    3.
    发明授权
    Power semiconductor device and preparation method thereof 有权
    功率半导体器件及其制备方法

    公开(公告)号：US09214419B2

    公开(公告)日：2015-12-15

    申请号：US14194502

    申请日：2014-02-28

    Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

    Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu

    IPC: H01L21/44 ,  H01L23/495 ,  H01L21/78 ,  H01L23/29 ,  H01L23/48 ,  H01L23/52

    CPC classification number: H01L23/49551 ,  H01L21/561 ,  H01L21/78 ,  H01L23/043 ,  H01L23/24 ,  H01L23/293 ,  H01L23/3114 ,  H01L23/492 ,  H01L23/49513 ,  H01L23/4952 ,  H01L23/49555 ,  H01L23/49562 ,  H01L23/49575 ,  H01L2224/73253

    Abstract: A preparation method for a power semiconductor device includes: providing a lead frame containing a plurality of chip mounting units, one side edge of a die paddle of each chip mounting unit is bent and extended upwardly and one lead connects to the bent side edge of the die paddle and extends in an opposite direction from the die paddle; attaching a semiconductor chip to the top surface of the die paddle; forming metal bumps on each electrode at the front of the semiconductor chip with a top end of each metal bump protruding out of a plane of the top surface of the lead; heating the metal bump and pressing a top end of each metal bump by a pressing plate forming a flat top end surface that is flush with the top surface of the lead; and cutting the lead frame to separate individual chip mounting units.

    Abstract translation: 一种功率半导体器件的制备方法，包括：提供包含多个芯片安装单元的引线框架，每个芯片安装单元的模板的一个侧边缘向上弯曲并向上延伸，并且一个引线连接到所述芯片安装单元的弯曲侧边缘 模具桨，并且在与模桨相反的方向上延伸; 将半导体芯片附接到所述管芯焊盘的顶表面; 在半导体芯片的前面的每个电极上形成金属凸块，每个金属凸块的顶端从引线的顶表面的平面突出; 加热金属凸块并通过压板压制每个金属凸块的顶端，该压板形成与引线顶表面齐平的平坦顶端表面; 并切割引线框架以分离各个芯片安装单元。

    PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP)
    7.
    发明申请
    PACKAGING METHOD OF MOLDED WAFER LEVEL CHIP SCALE PACKAGE (WLCSP) 有权
    模压水平切片尺寸包装（WLCSP）的包装方法

    公开(公告)号：US20130210195A1

    公开(公告)日：2013-08-15

    申请号：US13547358

    申请日：2012-07-12

    Applicant: Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

    Inventor： Yan Xun Xue ,  Hamza Yilmaz ,  Yueh-Se Ho ,  Jun Lu ,  Ping Huang ,  Lei Shi ,  Lei Duan ,  Yuping Gong

    IPC: H01L21/78

    CPC classification number: H01L21/563 ,  H01L23/3157 ,  H01L2224/73104 ,  H01L2224/83191 ,  H01L2924/13091 ,  H01L2924/00

    Abstract: A WLCSP method comprises: depositing a metal bump on bonding pads of chips; forming a first packaging layer at front surface of wafer to cover metal bumps while forming an un-covered ring at the edge of wafer to expose the ends of each scribe line located between two adjacent chips; thinning first packaging layer to expose metal bumps; forming a groove on front surface of first packaging layer along each scribe line by cutting along a straight line extended by two ends of scribe line exposed on front surface of un-covered ring; grinding back surface of wafer to form a recessed space and a support ring at the edge of the wafer; depositing a metal layer at bottom surface of wafer in recessed space; cutting off the edge portion of wafer; and separating individual chips from wafer by cutting through first packaging layer, the wafer and metal layer along groove.

    Abstract translation: WLCSP方法包括：在芯片的焊盘上沉积金属凸块; 在晶片的前表面形成第一包装层以覆盖金属凸块，同时在晶片边缘形成未覆盖的环，以露出位于两个相邻芯片之间的每个划线的端部; 稀释第一包装层以暴露金属凸块; 通过沿着未被覆盖的环的前表面上暴露的划线的两端延伸的直线切割沿着每个划线在第一包装层的前表面上形成凹槽; 研磨晶片的后表面以在晶片的边缘处形成凹陷空间和支撑环; 在凹陷空间中在晶片的底面沉积金属层; 切断晶片的边缘部分; 以及通过沿着沟槽切割第一包装层，晶片和金属层，从晶片分离单个芯片。

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