公开(公告)号：US09577087B2

公开(公告)日：2017-02-21

申请号：US13313583

申请日：2011-12-07

申请人： Yasuhiko Onishi ,  Akio Sugi

发明人： Yasuhiko Onishi ,  Akio Sugi

IPC分类号： H01L29/78 ,  H01L29/08 ,  H01L29/06 ,  H01L29/40 ,  H01L29/417

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/402 ,  H01L29/404 ,  H01L29/41741

摘要： A semiconductor apparatus that has a first parallel pn-layer formed between an active region and an n+-drain region. A peripheral region is provided with a second parallel pn-layer, which has a repetition pitch narrower than the repetition pitch of the first parallel pn-layer. An n−-surface region is formed between the second parallel pn-layer and a first main surface. On the first main surface side of the n−-surface region, a plurality of p-guard ring regions are formed to be separated from each other. A field plate electrode is connected electrically to the outermost p-guard ring region among the p-guard ring regions. A channel stopper electrode is connected electrically to an outermost peripheral p-region of the peripheral region.

摘要翻译： 一种半导体装置，其具有在有源区域和n + - 划分区域之间形成的第一并联pn层。 外围区域设置有第二平行pn层，其具有比第一并联pn层的重复间距窄的重复间距。 在第二平行pn层和第一主表面之间形成n表面区域。 在n面区域的第一主表面侧，形成多个p保护环区域以彼此分离。 场板电极电连接到保护环区域中的最外侧保护环区域。 通道阻挡电极电连接到周边区域的最外周边p区域。

公开(公告)号：US09339549B2

公开(公告)日：2016-05-17

申请号：US14378974

申请日：2013-02-21

申请人： Yasuhiko Onishi

发明人： Yasuhiko Onishi

IPC分类号： A61K31/337 ,  A61K38/13 ,  A61K47/36 ,  A61K47/32 ,  A61K47/48

CPC分类号： A61K47/36 ,  A61K31/337 ,  A61K38/13 ,  A61K47/32 ,  A61K47/61

摘要： A cationic graft-copolymer for a drug delivery system comprising a unit derived from a having a hydroxyl groups, namely, a cationic polysaccharide of the following formula (1) (C6H7O2(OH)3-a (OX)a)xH2O (1) and a unit derived from a polymerizable olefin compound of the following formula (2) (a, x, X, R4, R5, R6, and R7 are defined in claim 1-8); a process for preparing the same and a transfection reagent made therefrom.

摘要翻译： 一种用于药物递送系统的阳离子接枝共聚物，其包含衍生自具有羟基的单元，即下式（1）的阳离子多糖（C6H7O2（OH）3-a（OX）a）xH2O（1） 和由下式（2）（a，x，X，R4，R5，R6和R7定义）的可聚合烯烃化合物衍生的单元定义在权利要求1-8中。 其制备方法和由其制备的转染试剂。

公开(公告)号：US08735982B2

公开(公告)日：2014-05-27

申请号：US13290508

申请日：2011-11-07

申请人： Yasuhiko Onishi

发明人： Yasuhiko Onishi

IPC分类号： H01L29/66

CPC分类号： H01L29/7811 ,  H01L29/0619 ,  H01L29/0634 ,  H01L29/0638 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/402 ,  H01L29/404

摘要： A superjunction semiconductor device is disclosed which has, in the active section, a first alternating-conductivity-type layer which makes a current flow in the ON-state of the device and sustains a bias voltage in the OFF-state of the device. There is a second alternating-conductivity-type layer in a edge-termination section surrounding the active section. The width of a region of a second conductivity type in the second alternating-conductivity-type layer becomes narrower at a predetermined rate from the edge on the active section side toward the edge of the edge termination section. The superjunction semiconductor device facilitates manufacturing the edge-termination section which exhibits a high breakdown voltage and a high reliability for breakdown voltage through a process that exhibits a high mass-productivity.

摘要翻译： 公开了一种超级结半导体器件，其在有源部分中具有第一交变导电型层，其使电流流动在器件的导通状态并且在器件的截止状态下维持偏置电压。 在围绕有源部分的边缘终端部分中存在第二交替导电型层。 第二导电型层中的第二导电类型的区域的宽度以从有源部分侧边缘朝向边缘终止部分的边缘的预定速率变窄。 超级结半导体器件通过显示高批量生产率的工艺，有助于制造出具有高击穿电压和高击穿电压可靠性的边缘终端部分。

公开(公告)号：US07911020B2

公开(公告)日：2011-03-22

申请号：US12171193

申请日：2008-07-10

申请人： Yasushi Niimura ,  Takashi Kobayashi ,  Masanori Inoue ,  Yasuhiko Onishi

发明人： Yasushi Niimura ,  Takashi Kobayashi ,  Masanori Inoue ,  Yasuhiko Onishi

IPC分类号： H01L29/02

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/1095 ,  H01L29/404 ,  H01L29/41741 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor device has an active portion having at least one well region in a semiconductor layer, and a breakdown voltage maintaining structure surrounding the active portion. The maintaining structure includes a conductor layer over each of a plurality of guard rings with an insulating film interposed in between and connected to the respective guard ring. An inner side end portion of each conductor layer projects over the immediate adjacent inner side guard ring. The impurity concentration of the guard rings is set between the impurity concentrations of the semiconductor layer and the well regions. A field plate can extend over the innermost conductor layer with the insulating film interposed in between. The field plate is in contact with the outermost well region and is in contact with the first conductor layer. The outer side end of the field plate extends outwardly beyond an outer side end of the innermost conductor layer. With these arrangements, the guard rings can be shortened and the chip size can be reduced. Furthermore, the device can be made less susceptible to external charge.

摘要翻译： 半导体器件具有在半导体层中具有至少一个阱区的有源部分和围绕有源部分的击穿电压保持结构。 保持结构包括在多个保护环中的每一个上的导体层，绝缘膜介于其间并连接到相应的保护环。 每个导体层的内侧端部突出在紧邻的内侧保护环上。 保护环的杂质浓度设定在半导体层和阱区的杂质浓度之间。 场板可以在绝缘膜介于其间的最内侧的导体层上延伸。 场板与最外层区域接触并与第一导体层接触。 场板的外侧端部向外延伸超出最内侧导体层的外侧端部。 通过这些布置，可以缩短保护环，并且可以减小芯片尺寸。 此外，可以使该装置不易受到外部充电的影响。

公开(公告)号：US20090215167A1

公开(公告)日：2009-08-27

申请号：US12314394

申请日：2008-12-10

申请人： Yasuhiko Onishi

发明人： Yasuhiko Onishi

IPC分类号： C12N15/63

CPC分类号： C08L51/02 ,  C08F251/00 ,  C08F261/04

摘要： A cationic graft-copolymer for a non-viral gene delivery vector comprising a unit derived from a cationic derivative of a water-soluble linear polymers having a hydroxyl groups, namely, a cationic polysaccharide of the following formula (1) and the cationic derivative of polyvinylalcohol of the following formula (2) or the cationic derivative of the partial hydrolyzed polyvinylalcohol of the following formula (3) and a unit derived from a polymerizable olefin compound of the following formula (4) a process for preparing the same and a transfection reagent made therefrom.

摘要翻译： 一种用于非病毒基因递送载体的阳离子接枝共聚物，其包含衍生自具有羟基的水溶性线性聚合物的阳离子衍生物的单元，即下式（1）的阳离子多糖和阳离子衍生物 下式（2）的聚乙烯醇或下式（3）的部分水解聚乙烯醇的阳离子衍生物和由下式（4）的可聚合烯烃化合物衍生的单元及其制备方法和转染试剂 由此制成。

公开(公告)号：US07372111B2

公开(公告)日：2008-05-13

申请号：US11197751

申请日：2005-08-04

申请人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Masanori Inoue

发明人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Masanori Inoue

IPC分类号： H01L29/72

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/7802

摘要： The superjunction semiconductor device includes a drain drift section, which includes a first alternating conductivity type layer formed of first n-type regions and first p-type regions arranged alternately. The device also includes a peripheral section around the drain drift section, which includes a second alternating conductivity type layer formed of second n-type regions and second p-type regions arranged alternately. The peripheral section further includes a third alternating conductivity type layer in its surface portion. The third alternating conductivity type layer is formed of third n-type regions and third p-type regions arranged alternately. At least the peripheral section is configured to improve the avalanche withstanding capability over the entire device.

摘要翻译： 超级结半导体器件包括漏极漂移部分，其包括由第一n型区域和交替布置的第一p型区域形成的第一交变导电类型层。 该装置还包括围绕漏极漂移部分的周边部分，其包括由交替布置的第二n型区域和第二p型区域形成的第二交变导电类型层。 外围部分还包括在其表面部分中的第三交变导电类型层。 第三交变导电型层由交替布置的第三n型区域和第三p型区域形成。 至少外围部分被配置为提高整个设备上的雪崩承受能力。

公开(公告)号：US07235841B2

公开(公告)日：2007-06-26

申请号：US10973946

申请日：2004-10-26

申请人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Hitoshi Abe

发明人： Yasuhiko Onishi ,  Takeyoshi Nishimura ,  Yasushi Niimura ,  Hitoshi Abe

IPC分类号： H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L29/00

CPC分类号： H01L29/7811 ,  H01L29/0634 ,  H01L29/0653 ,  H01L29/0661 ,  H01L29/0696

摘要： A semiconductor device includes an active region, an alternating conductivity type layer, and an insulation region surrounding the alternating conductivity type layer provided in a periphery section as a voltage withstanding section. The insulation region is made of an insulator with the critical electric field strength higher than that of the semiconductor and reaches an n+-drain layer on the bottom surface side of the device from a surface on the side on which a surface structure section is formed. In the alternating conductivity type layer, the width of the p-type partition region adjacent to the insulation region is made narrower than the width of the p-type partition region not adjacent to the insulation region to ensure a balanced state of charges at the end of the drift section made up of the alternating conductivity type layer. A high breakdown voltage is ensured with the length of the periphery section shortened.

摘要翻译： 半导体器件包括有源区，交变导电类型层和围绕设置在周边部分中的交变导电类型层的绝缘区域作为耐压部分。 绝缘区域由临界电场强度高于半导体的绝缘体制成，并从设备侧面上的表面到达器件底面侧的n + 其形成表面结构部分。 在交变导电型层中，与绝缘区域相邻的p型分隔区域的宽度比不与绝缘区域相邻的p型分隔区域的宽度窄，以确保最终的电荷平衡状态 由交替导电型层构成的漂移部分。 确保周边部分的长度缩短的高击穿电压。

公开(公告)号：US06825537B2

公开(公告)日：2004-11-30

申请号：US10683868

申请日：2003-10-10

申请人： Susumu Iwamoto ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： H01L2976

CPC分类号： H01L29/7813 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/4238 ,  H01L29/7397

摘要： In a trench super junction semiconductor element having a parallel p-n junction layer 14 with n-drift regions 12 and p-partition regions 13, both extending in a depth direction, being alternately joined, a part 20 in a shape of a three-dimensional curved surface in the end portion of each of trenches is formed in a p-partition region 13. A section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface of the end portion of each of the trenches is made as a p+-region 21 in which an impurity concentration is higher than that in a section thereunder so that an electric field is increased at a boundary between the p+-region 21 and the n-drift region 12, thereby lessening electric field concentration to the part 20 in a shape of a three-dimensional curved surface of the end portion of the trench. Moreover, the section in the p-partition region 13 surrounding the part 20 in a shape of a three-dimensional curved surface in the end portion of the trench can be formed wider than the section thereunder. This inhibits lowering in a breakdown voltage and, along with this, increases reliability of a gate insulator film.

摘要翻译： 在具有平行pn结层14的沟槽超结半导体元件中，其具有n个漂移区域12和p分隔区域13，两者都在深度方向上延伸交替地接合，形成为三维弯曲形状的部分20 每个沟槽的端部中的表面形成在p分隔区域13中。在p分隔区域13中的每个的端部的三维曲面形状的部分20周围的部分 沟槽被制成为其中杂质浓度高于其下段的杂质浓度的ap +区域21，使得在p +区域21和n-漂移区域12之间的边界处的电场增加 从而减小了沟槽端部的三维曲面形状的部分20的电场浓度。 此外，在沟槽端部的三维曲面形状的围绕部分20的p分隔区域13中的部分可以形成得比其下面的部分更宽。 这抑制了击穿电压的降低，并且与此同时增加了栅极绝缘膜的可靠性。

公开(公告)号：US06756636B2

公开(公告)日：2004-06-29

申请号：US09844481

申请日：2001-04-27

申请人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

发明人： Yasuhiko Onishi ,  Tatsuhiko Fujihira ,  Susumu Iwamoto ,  Takahiro Sato

IPC分类号： H01L2976

CPC分类号： H01L29/1095 ,  H01L29/0634 ,  H01L29/0696 ,  H01L29/7816 ,  H01L2924/0002 ,  H01L2924/00

摘要： A lateral semiconductor device includes an alternating conductivity type layer for providing a first semiconductor current path in the ON-state of the device and for being depleted in the OFF-state of the device, that has an improved structure for realizing a high breakdown voltage in the curved sections of the alternating conductivity type layer.

摘要翻译： 横向半导体器件包括交替导电类型层，用于在器件的导通状态中提供第一半导体电流路径并且耗尽器件的截止状态，其具有用于实现高的击穿电压的改进的结构 交替导电型层的弯曲部分。

公开(公告)号：US06674126B2

公开(公告)日：2004-01-06

申请号：US10073671

申请日：2002-02-11

申请人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

发明人： Susumu Iwamoto ,  Tatsuhiko Fujihira ,  Katsunori Ueno ,  Yasuhiko Onishi ,  Takahiro Sato ,  Tatsuji Nagaoka

IPC分类号： A01L29772

CPC分类号： H01L29/7802 ,  H01L29/0634

摘要： A semiconductor device facilitates obtaining a higher breakdown voltage in the portion of the semiconductor chip around the drain drift region and improving the avalanche withstanding capability thereof. A vertical MOSFET according to the invention includes a drain layer; a drain drift region on drain layer, drain drift region including a first alternating conductivity type layer; a breakdown withstanding region (the peripheral region of the semiconductor chip) on drain layer and around drain drift region, breakdown withstanding region providing substantially no current path in the ON-state of the MOSFET, breakdown withstanding region being depleted in the OFF-state of the MOSFET, breakdown withstanding region including a second alternating conductivity type layer, and an under region below a gate pad, and the under region including a third alternating conductivity type layer.

摘要翻译： 半导体器件有助于在漏极漂移区周围的半导体芯片的部分中获得更高的击穿电压并且提高其雪崩耐受能力。 根据本发明的垂直MOSFET包括漏极层; 漏极层上的漏极漂移区，包括第一交替导电型层的漏极漂移区; 在漏极层和漏极漂移区域周围的击穿耐受区域（半导体芯片的外围区域），在MOSFET的导通状态基本上不提供电流路径的击穿承受区域，击穿耐受区域在断开状态 MOSFET，包括第二交替导电类型层的击穿耐受区域和栅极焊盘下方的下部区域，以及包括第三交变导电类型层的下部区域。