Phase locked loop circuit
    2.
    发明授权
    Phase locked loop circuit 失效
    锁相环电路

    公开(公告)号:US5117204A

    公开(公告)日:1992-05-26

    申请号:US708758

    申请日:1991-05-31

    CPC分类号: H03L7/085 H03L7/18

    摘要: By using an EIP source lock counter, a frequency of a Gunn oscillator is stabilized. This increases the frequency stability of a circuit. An oscillation output of the Gunn Oscillator is supplied to the EIP source lock counter, and a phase lock signal indicative of a phase shift of the oscillation frequency from the EIP source lock counter relative to a preset reference frequency is supplied to a driver circuit. The driver circuit includes level shift circuit which level-shifts the phase lock signal thereof. A phase compensation circuit in the driver circuit boosts a gain as well as advances a phase at a high frequency region. The current amplifier circuit amplifies a current amplitude of the output of the level shift circuit, and the amplified output therefrom controls an oscillation frequency of the Gunn oscillator using negative feedback.

    摘要翻译: 通过使用EIP源锁定计数器,Gunn振荡器的频率稳定。 这增加了电路的频率稳定性。 将GUN振荡器的振荡输出提供给EIP源锁定计数器,并且将指示来自EIP源锁定计数器的振荡频率相对于预设参考频率的相位锁定信号提供给驱动器电路。 驱动器电路包括对其锁相信号进行电平移位的电平移位电路。 驱动电路中的相位补偿电路增益增益以及在高频区域前进相位。 电流放大器电路放大电平移位电路的输出的电流幅度,并且其放大的输出使用负反馈来控制耿氏振荡器的振荡频率。

    One-time PROM microcomputer
    3.
    发明授权
    One-time PROM microcomputer 失效
    一次性PROM微电脑

    公开(公告)号:US5398208A

    公开(公告)日:1995-03-14

    申请号:US246713

    申请日:1994-05-20

    申请人: Yasuhiko Sakamoto

    发明人: Yasuhiko Sakamoto

    CPC分类号: G11C17/18 G11C5/143

    摘要: An OTP microcomputer of the present invention includes: a PROM 14 having a terminal for receiving signals from a voltage supply Vpp that allows a program to be written therein; a MOS transistor to be used as a resistance or a resistance cable containing a pull-up resistance R4, and an input terminal 11 connected to both the terminal of the PROM and a logic circuit of the microcomputer and connected with the drain of the MOS transistor or one end of the resistance R4. In this arrangement, when a microcomputer mode in which the OTP microcomputer is operated as a normal microcomputer is selected, a voltage Vcc (.vertline.Vpp.vertline.>.vertline.Vcc.vertline.) of a device power supply provided inside the circuit of the microcomputer is supplied to the source of the MOS transistor or the other end of the resistance R4. On the other hand, when an OTP mode in which the PROM is written in with a program is selected, the voltage Vpp of the power supply for allowing a program to be written in is supplied to the source of the MOS transistor or the other end of the resistance R4.

    摘要翻译: 本发明的OTP微计算机包括:具有端子的PROM14,用于从电压源Vpp接收信号,该电压允许在其中写入程序; 用作电阻的MOS晶体管或包含上拉电阻R4的电阻电缆,以及连接到PROM的端子和微型计算机的逻辑电路并与MOS晶体管的漏极连接的输入端子11 或电阻R4的一端。 在这种布置中,当选择OTP微型计算机作为普通微型计算机操作的微型计算机模式时,设置在微计算机的电路内部的装置电源的电压Vcc(| Vpp |> | Vcc |)被提供给 MOS晶体管的源极或电阻R4的另一端。 另一方面,当选择使用程序写入PROM的OTP模式时,将用于允许写入程序的电源的电压Vpp提供给MOS晶体管的源极或另一端 的电阻R4。

    Time division multiplexing communication system

    公开(公告)号:US3643031A

    公开(公告)日:1972-02-15

    申请号:US3643031D

    申请日:1969-09-15

    IPC分类号: H04J3/16 H04B7/15 H04B7/212

    CPC分类号: H04B7/2123

    摘要: A time division multiplexing communication system has a plurality of stations and a switching station. Two of the stations communicate with each other via the switching station by utilizing signals comprising a block having a plurality of words each comprising a plurality of frames which are bursts of a constant time length. Each of the stations comprises channel rearrangement control means for rearranging ground channels to satellite channels and for rearranging satellite channels to ground channels in accordance with informations from an order data channel. Burst synchronism control means connected to the channel rearrangement control means provides the timing of transmission and reception of bursts. Order word controls means connected to the channel rearrangement control means receives command data, provides an order data channel, changes the command data to the format of the order data channel, transmits the format to the other stations and assembles a word from the order data channel information received from the other stations. Command control means is connected to the order word control means, the channel rearrangement control means and the burst synchronism control means and is controlled by a program to discriminate the condition of operation of the channel rearrangement control means, the burst synchronism control means and the order word control means, and supplies thereto command data commanding the means to operate. The order word control means transfers the work assembled from the order data channel received from the other stations to the command control unit when the word is directed to the station. Block synchronism controlling means controls the timing of transmission and reception of the blocks and provides block synchronism for blocks of period TB determined in accordance with the equations nTB > OR = Tl +TP and (n- 1)TB

    Production of imidazole derivatives and novel intermediates of the derivatives
    5.
    发明授权
    Production of imidazole derivatives and novel intermediates of the derivatives 失效
    咪唑衍生物的生产和衍生物的新型中间体

    公开(公告)号:US06951944B2

    公开(公告)日:2005-10-04

    申请号:US10501801

    申请日:2003-02-18

    IPC分类号: C07D401/06 C07F9/6506

    摘要: An improvement in the production of imidazole derivatives including histamine H3 agonist immepip and histamine H3 antagonist VUF4929. Desired imidazole derivatives can be easily obtained in high yield by using novel intermediates represented by the general formula (I): (I) wherein R1 is an amino-protecting group; R2 and R3 are each independently hydrogen, lower alkyl, or hydroxylated lower alkyl; R4 is lower alkyl, halogenated lower alkyl, or substituted or unsubstituted phenyl; and A is C1-3 alkylene

    摘要翻译: 包括组胺H 3激动剂immepip和组胺H 3 N拮抗剂VUF4929的咪唑衍生物的生产的改进。 通过使用由通式(I)表示的新型中间体,可以容易地获得所需的咪唑衍生物:(I)其中R 1是氨基保护基; R 2和R 3各自独立地为氢,低级烷基或羟基化的低级烷基; R 4是低级烷基,卤代低级烷基或取代或未取代的苯基; 且A为C 1-3亚烷基

    Process for producing piperazinesulfonamide derivatives and salts thereof
    6.
    发明授权
    Process for producing piperazinesulfonamide derivatives and salts thereof 失效
    哌嗪磺酰胺衍生物及其盐的制备方法

    公开(公告)号:US06172228B2

    公开(公告)日:2001-01-09

    申请号:US09453223

    申请日:1999-12-03

    IPC分类号: C07D40106

    CPC分类号: C07D295/088 C07D213/38

    摘要: A process for advantageously preparing a piperazinesulfonamide derivative represented by the general formula (III): wherein R1 is hydrogen atom, a straight or branched chain alkyl group having 1 to 6 carbon atoms, an alkoxy group having 1 to 4 carbon atoms, a halogen atom, hydroxyl group, trifluoromethyl group, nitro group or amino group; R2 is a phenyl group which may have as substituents on its phenyl ring 1 to 3 groups selected from the group consisting of an alkyl group having 1 to 4 carbon atoms, an alkoxy group having 1 to 4 carbon atoms, a halogen atom, hydroxyl group, trifluoromethyl group, nitro group and amino group, 2-pyridyl group, 3-pyridyl group or 4-pyridyl group; each of R3 and R4 is independently hydrogen atom, a straight or branched chain alkyl group having 1 to 6 carbon atoms, a hydroxyalkyl group having 1 to 4 carbon atoms, a cycloalkyl group having 3 to 8 carbon atoms, or a phenyl group which may be substituted; and Y is an alkylene group having 1 to 12 carbon atoms, and a salt thereof.

    摘要翻译: 一种有利地制备由通式(III)表示的哌嗪磺酰胺衍生物的方法:其中R1是氢原子,具有1至6个碳原子的直链或支链烷基,具有1至4个碳原子的烷氧基,卤素原子 ,羟基,三氟甲基,硝基或氨基; R2是可以在其苯环上具有取代基的苯基,其选自具有1至4个碳原子的烷基,具有1至4个碳原子的烷氧基,卤素原子,羟基 三氟甲基,硝基和氨基,2-吡啶基,3-吡啶基或4-吡啶基; R 3和R 4各自独立地为氢原子,具有1至6个碳原子的直链或支链烷基,具有1至4个碳原子的羟基烷基,具有3至8个碳原子的环烷基或苯基, 被替代 Y为碳原子数1〜12的亚烷基及其盐。

    3-Aminocarbonyl-1,4-dihydropyridine-5-carboxylic acid compounds, and
pharmaceutical composition containing the same
    7.
    发明授权
    3-Aminocarbonyl-1,4-dihydropyridine-5-carboxylic acid compounds, and pharmaceutical composition containing the same 失效
    3-氨基羰基-1,4-二氢吡啶-5-羧酸化合物,以及含有它们的药物组合物

    公开(公告)号:US4874773A

    公开(公告)日:1989-10-17

    申请号:US239005

    申请日:1988-08-30

    CPC分类号: C07D211/90

    摘要: Novel 3-aminocarbonyl-1,4-dihydropyridine-5-carboxylic acid compounds of the formula: ##STR1## wherein R.sup.1 is H, C.sub.1-5 alkyl, C.sub.2-5 alkenyl, C.sub.3.5 alkynyl, C.sub.3-8 cycloalkyl, R.sup.2 is C.sub.1-10 alkyl, and the NO.sub.2 group is substituted at ortho- or meta-position, provided that when the NO.sub.2 group is substituted at ortho-position and R.sup.2 is methyl, R.sup.1 is C.sub.3-5 alkyl, C.sub.2-5 alkenyl, C.sub.3-5 alkynyl, or C.sub.3-8 cycloalkyl, and when the NO.sub.2 group is substituted at meta-position and R.sup.1 is H, R.sup.2 is C.sub.3-10 alkyl, which have excellent hypotensive, vasodilating activities and are useful for the prophylaxis and treatment of hypertension, ischemic heart diseases and cerebral and peripheral circulation diseases.

    摘要翻译: 新颖的下式的3-氨基羰基-1,4-二氢吡啶-5-羧酸化合物:其中R 1是H,C 1-5烷基,C 2-5烯基,C 3-5炔基,C 3-8环烷基 R2是C1-10烷基,并且NO2基团在邻位或间位被取代,条件是当NO 2基团在邻位被取代且R2是甲基时,R1是C3-5烷基,C2-5烯基 ,C3-5炔基或C3-8环烷基,当NO2基团在间位被取代且R1为H时,R2为C3-10烷基,具有优异的降血压,血管舒张活性,可用于预防和治疗 的高血压,缺血性心脏病和脑和周围循环疾病。

    Faulty-memory processing method and apparatus
    8.
    发明授权
    Faulty-memory processing method and apparatus 失效
    故障存储器处理方法和装置

    公开(公告)号:US4617660A

    公开(公告)日:1986-10-14

    申请号:US587518

    申请日:1984-03-08

    申请人: Yasuhiko Sakamoto

    发明人: Yasuhiko Sakamoto

    CPC分类号: G06F11/1024

    摘要: A faulty-memory processing method and apparatus in a data processing system which executes a time-sharing data process with breaks. Hard error which may exist in a cell in a normal memory is detected by using an error correction circuit. After correcting an error in information read out from a detected hard-error cell in the normal memory, information including the above corrected information with respect to the detected hard-error cell is transcribed into a relief memory. The above correction and transcription is executed during the breaks in the time-sharing data process.

    摘要翻译: 数据处理系统中的故障存储器处理方法和装置,其执行具有中断的分时数据处理。 通过使用纠错电路来检测可能存在于正常存储器中的单元中的硬错误。 在校正从正常存储器中的检测到的硬错误单元读出的信息中的错误之后,将包括上述校正信息的关于检测到的硬错误单元的信息转录为浮动存储器。 上述修正和转录在分时数据处理中断期间执行。

    PLL clock signal generation circuit
    10.
    发明申请
    PLL clock signal generation circuit 有权
    PLL时钟信号发生电路

    公开(公告)号:US20050099235A1

    公开(公告)日:2005-05-12

    申请号:US10983649

    申请日:2004-11-09

    摘要: A PLL clock signal generation circuit comprising a phase comparator, a charge pump circuit, a filter circuit, a voltage control oscillator and a divider, wherein a multiple rate control circuit is further included which detects a state of the reference voltage (output from a filter circuit) and controls a change of a multiple rate of a divider according to a state of the detected reference voltage. The multiple rate control circuit further outputs control signal LPFOUT for changing a multiple rate so that the PLL clock signal generation circuit does not deviate from a region capable of locking when being detected of deviation from the region capable of locking by detecting the state of reference voltage.

    摘要翻译: 一种PLL时钟信号发生电路,包括相位比较器,电荷泵电路,滤波电路,压控振荡器和分频器,其中还包括多速率控制电路,其检测参考电压的状态(从滤波器输出 电路),并且根据检测到的参考电压的状态来控制分频器的多速率的变化。 多速率控制电路还输出用于改变多重速率的控制信号LPFOUT,使得当通过检测参考电压的状态检测到与能够锁定的区域的偏差时,PLL时钟信号发生电路不会偏离可以锁定的区域 。