公开(公告)号：US07167933B2

公开(公告)日：2007-01-23

申请号：US10649578

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu

发明人： Masahiro Kimura ,  Yasunori Fukumitsu

IPC分类号： G06F3/00 ,  G06F13/00 ,  B41J2/01 ,  B41J29/38

CPC分类号： G06F13/28

摘要： A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.

摘要翻译： 数据传送装置具有ASIC（专用集成电路），并且ASIC包括耦合以能够传送数据的接口单元，头控制单元，接收缓冲器单元和DECU。 DECU包括具有用于在压缩记录数据上执行硬件开发的解码电路的开发处理控制器，以及存储显影记录数据的行缓冲器。 DECU和头部控制单元通过内部总线1B耦合以执行数据传送。

公开(公告)号：US07167932B2

公开(公告)日：2007-01-23

申请号：US10649296

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： G06F13/00 ,  H04N7/12

CPC分类号： G06K15/102 ,  G06K15/00

摘要： Compressed recording data is DMA-transferred to a receiving buffer unit via a system bus one word each. It is DMA-transferred from the receiving buffer unit to a DECU via the system bus. It is developed based on hardware by a decode circuit in the DECU, and stored in a line buffer. It is DMA-transferred to a local memory via a local bus when it reaches predetermined bytes. The recording data stored in the local memory is DMA-transferred to the DECU via the local bus, DMA-transferred to a head controlling unit and DMA-transferred to a recording head.

摘要翻译： 压缩记录数据通过系统总线DMA传输到接收缓冲单元，每个字母一个字。 它通过系统总线从接收缓冲单元DMA传输到DECU。 它是通过DECU中的解码电路基于硬件开发的，并存储在行缓冲区中。 当达到预定字节时，DMA通过本地总线传输到本地存储器。 存储在本地存储器中的记录数据通过本地总线DMA传送到DECU，DMA传送到头控制单元，DMA传送到记录头。

公开(公告)号：US20050038929A1

公开(公告)日：2005-02-17

申请号：US10649228

申请日：2003-10-22

申请人： Yasunori Fukumitsu ,  Masahiro Kimura

发明人： Yasunori Fukumitsu ,  Masahiro Kimura

IPC分类号： B41J2/01 ,  G06F3/00 ,  G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06K15/10 ,  H04L12/00 ,  H04L12/40

CPC分类号： G06K15/102

摘要： A data transferring apparatus for transferring liquid ejection data, has a decode unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit, wherein the line buffer comprises two faces of buffer areas in order to store the developed data, the developed liquid ejection data is sequentially stored in a first face of the buffer areas, while the developed liquid ejection data is sequentially stored in a second face of the buffer areas when the developed data of predetermined words has been accumulated, and the developed liquid ejection data is stored in a first face one word each, while the liquid ejection data already developed in a second face is simultaneously transferred to an external memory one word each.

摘要翻译： 一种用于传送液体喷射数据的数据传送装置，具有一个解码单元，该解码单元具有可对液体喷射数据执行硬件开发的解码电路，用于存储由单元单元开发的液体喷射数据的行缓冲器，以及一个压缩数据输入单元， 从外部部分到解码电路的液体喷射数据，其中线缓冲器包括缓冲区域的两个面以存储显影数据，显影液体喷射数据被顺序地存储在缓冲区域的第一面中，而 显影的液体喷射数据被顺序地存储在缓冲区域的第二面中，当已经累积了预定字的显影数据时，显影的液体喷射数据以第一面每个存储，而液体喷射数据已经在 第二面同时被传送到外部存储器一个字。

公开(公告)号：US20060187248A1

公开(公告)日：2006-08-24

申请号：US11408280

申请日：2006-04-19

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

公开(公告)号：US07458652B2

公开(公告)日：2008-12-02

申请号：US11408280

申请日：2006-04-19

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

摘要翻译： 如果与记录数据无关的数据被存储在存储在接收缓冲器单元中的游程长度压缩记录数据的头字数据的较低地址中，则包含头字节的字数据的低位地址的不相关字节数据 数据由解码电路开发的掩码无效。 否则，关于作为DMA传送目的地的本地存储器的位图区域，传输地址由开发处理控制器以存储在行缓冲器中的开发的记录数据的每个单词的DECU单独设置，以便数据 将一行排列并存储在垂直方向上，或者一行的数据依次存储在图像1和图像2中。 否则，关于开发处理控制器，当由解码电路开发的记录数据存储在行缓冲器中时，在行缓冲器的第0字节空闲的状态下从第一字节存储。

公开(公告)号：US07188197B2

公开(公告)日：2007-03-06

申请号：US10649228

申请日：2003-10-22

申请人： Yasunori Fukumitsu ,  Masahiro Kimura

发明人： Yasunori Fukumitsu ,  Masahiro Kimura

IPC分类号： G06F13/00 ,  G06F13/28 ,  G06F15/00

CPC分类号： G06K15/102

摘要： A data transferring apparatus for transferring liquid ejection data has a decoding unit having a decode circuit, which can perform hardware development on liquid ejection data, a line buffer for storing the liquid ejection data developed by a word unit and a compressed data inputting unit for transferring the liquid ejection data from an external part to the decode circuit.

摘要翻译： 用于传送液体喷射数据的数据传送装置具有解码单元，该解码单元具有可对液体喷射数据执行硬件开发的解码电路，用于存储由单元单元开发的液体喷射数据的行缓冲器和用于传送的压缩数据输入单元 从外部部分到解码电路的液体喷射数据。

公开(公告)号：US07177955B2

公开(公告)日：2007-02-13

申请号：US10649231

申请日：2003-08-26

申请人： Yasunori Fukumitsu ,  Masahiro Kimura

发明人： Yasunori Fukumitsu ,  Masahiro Kimura

IPC分类号： G06F13/00

CPC分类号： G06K15/102 ,  G06K15/18 ,  G06K15/181 ,  G06K15/1822

摘要： Record controlling data received by an interface unit is transferred to a change controlling block, and transferred to a head analyzing block so that analysis of its head can be performed. In case the data following the head is a command, it is stored in a command storing register, and in case of compressed recording data, it is transferred to a data transfer controlling block. A MPU accesses the command storing register to analyze the command. The compressed recording data is stored in a FIFO memory via a first dedicated bus from the data transfer controlling block, and transferred to a DECU via a second dedicated bus.

摘要翻译： 由接口单元接收的记录控制数据被传送到改变控制块，并被传送到头部分析块，从而可以执行其头部的分析。 在头部之后的数据是命令的情况下，将其存储在命令存储寄存器中，并且在压缩记录数据的情况下将其传送到数据传送控制块。 MPU访问命令存储寄存器来分析命令。 压缩记录数据通过第一专用总线从数据传送控制块存储在FIFO存储器中，并通过第二专用总线传送到DECU。

公开(公告)号：US20050001862A1

公开(公告)日：2005-01-06

申请号：US10649578

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu

发明人： Masahiro Kimura ,  Yasunori Fukumitsu

IPC分类号： B41J29/38 ,  G06F13/00 ,  G06F13/28 ,  G06F13/36 ,  G06K15/10 ,  H04L12/00 ,  H04L12/40

CPC分类号： G06F13/28

摘要： A data transferring apparatus has an ASIC (Application Specific Integrated Circuit), and the ASIC incorporates an interface unit, a head controlling unit, a receiving buffer unit and a DECU, which are coupled to be capable of transferring data. The DECU incorporates a development processing controller having a decode circuit for performing hardware development on compressed recording data, and a line buffer storing developed recording data. The DECU and the head controlling unit are coupled by an internal bus IB in order to perform data transfer.

摘要翻译： 数据传送装置具有ASIC（专用集成电路），并且ASIC包括耦合以能够传送数据的接口单元，头控制单元，接收缓冲器单元和DECU。 DECU包括具有用于在压缩记录数据上执行硬件开发的解码电路的开发处理控制器，以及存储显影记录数据的行缓冲器。 DECU和头部控制单元通过内部总线1B耦合以执行数据传送。

公开(公告)号：US07083244B2

公开(公告)日：2006-08-01

申请号：US10649545

申请日：2003-08-26

申请人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

发明人： Masahiro Kimura ,  Yasunori Fukumitsu ,  Yasuhisa Yamamoto ,  Masahiro Igarashi

IPC分类号： B41J29/38 ,  B41J2/205 ,  G03F3/08

CPC分类号： G06K15/102 ,  G06F13/28

摘要： If data, which is irrelevant to recording data, is stored in a lower address of head word data of the run length compressed recording data stored in a receiving buffer unit, the irrelevant byte data of the lower address of the word data including the head byte data is nullified by masking to be developed by a decode circuit. Otherwise, in regard to a bitmap area of a local memory which is a DMA transfer destination, transfer addresses are individually set by a development processing controller in a DECU per one word of the developed recording data stored in the line buffer in order that data of one line is arranged and stored in a vertical direction, or data of one line is stored in image 1 and image 2 in turn. Otherwise, in regard to the development processing controller, when the recording data developed by the decode circuit is stored in the line buffer, it is stored from a first byte in a state where a 0-th byte of the line buffer is vacant.

摘要翻译： 如果与记录数据无关的数据被存储在存储在接收缓冲器单元中的游程长度压缩记录数据的头字数据的较低地址中，则包含头字节的字数据的低位地址的不相关字节数据 数据由解码电路开发的掩码无效。 否则，关于作为DMA传送目的地的本地存储器的位图区域，传输地址由开发处理控制器以存储在行缓冲器中的开发的记录数据的每个单词的DECU单独设置，以便数据 将一行排列并存储在垂直方向上，或者一行的数据依次存储在图像1和图像2中。 否则，关于开发处理控制器，当由解码电路开发的记录数据存储在行缓冲器中时，在行缓冲器的第0字节空闲的状态下从第一字节存储。

公开(公告)号：US4657805A

公开(公告)日：1987-04-14

申请号：US749623

申请日：1985-06-13

申请人： Yasunori Fukumitsu ,  Mitsuo Kohno

发明人： Yasunori Fukumitsu ,  Mitsuo Kohno

IPC分类号： B32B27/30 ,  G03F1/00 ,  G03F1/62 ,  H01L21/027 ,  B32B7/02

CPC分类号： G03F1/62 ,  B32B27/30 ,  Y10T428/24967 ,  Y10T428/31544

摘要： In a dust cover for photomask reticle purposes which consists essentially of a supporting frame and a thin film bonded to a surface of the frame, the dust cover is improved in transparency by constructing at least the outermost layers of the thin film with thin films of a fluoropolymer which exhibits an average transmittance of at least 90% for rays of wavelengths from 240 to 290 nm and an average transmittance of at least 93.5% for rays of wavelengths from 290 to 500 nm, when having a thickness of 10 .mu.m, and has a refractive index of up to 1.42.

摘要翻译： PCT No.PCT / JP84 / 00485 Sec。 371日期：1985年6月13日 102（e）1985年6月13日PCT PCT Filed于1984年10月12日。在用于光掩模掩模版目的的防尘罩中，基本上由支撑框架和结合到框架表面的薄膜组成，防尘罩被改进 通过用含氟聚合物的薄膜构成至少最外层的薄膜，其透射率对于240〜290nm的波长的平均透射率至少为90％，平均透射率至少为93.5％，对于 波长为290〜500nm，厚度为10μm，折射率高达1.42。