公开(公告)号：US06788698B1

公开(公告)日：2004-09-07

申请号：US09533592

申请日：2000-03-23

申请人： Ryouichi Bandai ,  Kenji Sakaue ,  Yasuo Unekawa ,  Yuichi Miyazawa

发明人： Ryouichi Bandai ,  Kenji Sakaue ,  Yasuo Unekawa ,  Yuichi Miyazawa

IPC分类号： H04L1228

CPC分类号： H04L49/3081 ,  H04L12/5601 ,  H04L49/30 ,  H04L2012/5651 ,  H04L2012/5682

摘要： It is an object of the present invention to provide a data switching method capable of impartially selecting a plurality of input ports by a simple circuit configuration. The data switching method according to the present invention includes an up-counter, a down-counter, a counter selecting circuit for selecting either of a counted value by the up-counter or a counted value by the down-counter, a port selecting circuit for selecting one of a plurality of input ports based on an output from the counter selecting circuit, and a buffer for accumulating a packet supplied from the input port selected by the port selecting circuit. The port selecting circuit alternately selects the up-counter and the down-counter to switch the ascending order and the descending order of the import priority of the input ports at every time the packet is imported, thereby impartially selecting each of the input ports.

摘要翻译： 本发明的目的是提供一种能够通过简单的电路配置公正地选择多个输入端口的数据切换方法。 根据本发明的数据交换方法包括：递增计数器，递减计数器，用于通过递增计数器选择计数值中的任何一个的计数器选择电路或通过递减计数器选择计数值的计数器选择电路;端口选择电路 用于基于来自计数器选择电路的输出来选择多个输入端口中的一个，以及用于累加由端口选择电路选择的输入端口提供的分组的缓冲器。 端口选择电路交替地选择递增计数器和递减计数器，以在每次输入数据包时切换输入端口的导入优先级的升序和降序，从而公正地选择每个输入端口。

公开(公告)号：US20070066254A1

公开(公告)日：2007-03-22

申请号：US11532346

申请日：2006-09-15

申请人： Koji Tsuchie ,  Mototsugu Hamada ,  Minoru Namekata ,  Yasuo Unekawa

发明人： Koji Tsuchie ,  Mototsugu Hamada ,  Minoru Namekata ,  Yasuo Unekawa

IPC分类号： H04B1/18

CPC分类号： H04B1/28 ,  H04B1/0014 ,  H04B1/0032

摘要： An analog signal processing circuit including: a frequency conversion unit for receiving a plurality of radio frequency signals having different center frequencies or a plurality of radio frequency signals having the same center frequencies but different amplitude-characteristics or phase-characteristics and converting the frequencies of the signals; a frequency selection unit for selecting a signal output from the frequency conversion unit at a predetermined band width; and an addition unit for adding a plurality of signals output from the frequency selection unit is provided.

摘要翻译： 一种模拟信号处理电路，包括：频率转换单元，用于接收具有不同中心频率的多个射频信号或具有相同中心频率但具有不同幅度特性或相位特性的多个射频信号，并将 信号; 频率选择单元，用于以预定的频带宽度选择从频率转换单元输出的信号; 并且提供用于添加从频率选择单元输出的多个信号的加法单元。

公开(公告)号：US5815499A

公开(公告)日：1998-09-29

申请号：US679492

申请日：1996-07-12

申请人： Yasuo Unekawa

发明人： Yasuo Unekawa

IPC分类号： H04Q3/00 ,  H04L12/775 ,  H04L12/801 ,  H04L12/851 ,  H04L12/911 ,  H04L12/931 ,  H04L12/933 ,  H04L12/54

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309

摘要： The proposed address generating circuit of an ATM (asynchronous transfer mode) switch can support a plurality of service classes by use of a single LSI under such a management that the cell buffers are divided for each service class. That is, an address generating circuit of shared buffer type ATM switch for an ATM switch system comprises a plurality of address generating units (5) each for storing a routing tag indicative of a cell output port, an address, and class data indicative of a service class of each of data cells stored in shared cell buffers. When data cells are inputted to and outputted from the shared cell buffers, the routing tags and the addresses of the address generating units (5) each having matching cell class data are selected and used.

摘要翻译： 所提出的ATM（异步传输模式）交换机的地址产生电路可以通过使用单个LSI来支持多个服务等级，这种管理使得针对每个服务类划分单元缓冲区。 也就是说，用于ATM交换系统的共享缓冲型ATM交换机的地址产生电路包括多个地址生成单元（5），每个地址生成单元用于存储指示单元输出端口的路由标签，地址和表示 存储在共享单元缓冲区中的每个数据单元的服务类。 当数据单元被输入到共享单元缓冲器并从共享单元缓冲器输出时，选择并使用每个具有匹配单元类数据的路由标签和地址生成单元（5）的地址。

公开(公告)号：US6011713A

公开(公告)日：2000-01-04

申请号：US995769

申请日：1997-12-22

申请人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

发明人： Fumiyuki Yamane ,  Tadahiro Kuroda ,  Toshinari Takayanagi ,  Masataka Matsui ,  Yasuo Unekawa ,  Tetsu Nagamatsu

IPC分类号： G11C11/412 ,  G11C11/419 ,  H01L21/8244 ,  H01L27/11 ,  G11C11/00

CPC分类号： G11C11/419

摘要： A semiconductor memory includes a memory cell including inverters (IN1, IN2), control transistors (T3, T4) that control the potential of a ground side terminal (N3) connected to the memory cell, and transfer transistors T1 and T2 that control transfer of data from bit lines (BL, /BL) to the memory cell. In writing data, the control transistors raise the potential of the ground side terminal (N3) to be higher than the ground potential by a predetermined potential. After the transfer transistors transfer data having a potential difference smaller than a potential difference between the power supply potential and the ground potential from the bit lines (BL, /BL) to the memory cell, and cause the memory cell to hold the data, the potential of the ground side terminal (N3) is decreased to the ground potential to write data. Since data written in the memory cell suffices to have a potential difference smaller than the potential difference between the power supply potential and the ground potential, the time required to drive the bit line having a large load capacitance is shortened, the power consumption is decreased, and the power consumption necessary for writing data in the memory cell is reduced.

摘要翻译： 半导体存储器包括：存储单元，包括反相器（IN1，IN2），控制与存储单元连接的接地侧端子（N3）的电位的控制晶体管（T3，T4）;以及控制晶体管T1和T2， 从位线（BL，/ BL）到存储单元的数据。 在写入数据时，控制晶体管将地侧端子（N3）的电位提高到高于接地电位预定电位。 在转移晶体管将具有比位线（BL，/ BL）的电源电位和接地电位之间的电位差的电位差的数据传送到存储单元之后，使存储单元保持数据， 接地侧端子（N3）的电位降低到接地电位以写入数据。 由于写入存储单元的数据足以具有比电源电位和接地电位之间的电位差小的电位差，所以驱动具有大负载电容的位线所需的时间缩短，功耗降低， 并且减少了在存储单元中写入数据所需的功耗。

公开(公告)号：US5822316A

公开(公告)日：1998-10-13

申请号：US680433

申请日：1996-07-15

申请人： Yasuo Unekawa

发明人： Yasuo Unekawa

IPC分类号： H04Q3/00 ,  H04L12/741 ,  H04L12/879 ,  H04L12/931 ,  H04L12/933 ,  H04L12/56

CPC分类号： H04L12/5601 ,  H04L49/108 ,  H04L49/309

摘要： The proposed address generating circuit of a shared-buffer type ATM (asynchronous transfer mode) switch adopts such an address management method that the ports multi-plexed by time division for each input link can be switched to each output link through time division multiplexing. The address generating circuit of shared-buffer type ATM switch used for an ATM switching system comprises a plurality of address generating units (4) each for storing an address, port data and output link data of a cell stored in each shared buffer in time series manner; two port pointer registers (8a, 8b, 8c, . . . ) for storing data indicative of a current output port for each output link; and a port list table (9) for storing data of ports accommodated in each output link.

摘要翻译： 共享缓冲型ATM（异步传输模式）交换机的所提出的地址产生电路采用这样的地址管理方法，即通过时分复用将每个输入链路通过时分多路复用的端口切换到每个输出链路。 用于ATM交换系统的共享缓冲型ATM交换机的地址产生电路包括多个地址生成单元（4），每个地址生成单元用于按时间序列存储存储在每个共享缓冲器中的单元的地址，端口数据和输出链接数据 方式; 两个端口指针寄存器（8a，8b，8c ...），用于存储指示每个输出链路的当前输出端口的数据; 以及用于存储容纳在每个输出链路中的端口的数据的端口列表表（9）。

公开(公告)号：US5706425A

公开(公告)日：1998-01-06

申请号：US378234

申请日：1995-01-26

申请人： Yasuo Unekawa

发明人： Yasuo Unekawa

IPC分类号： G06F11/30 ,  G06F13/00 ,  H04Q11/04

CPC分类号： H04Q11/0478 ,  H04L2012/565 ,  H04L2012/5652

摘要： A timeout process circuit for performing a timeout detection process incorporated in a receiver, having a timer for incrementing time data indicating a current time, a memory including data table to store a reception time of the cell most recently received by the receiver, a register for storing a timeout value indicating a maximum permitted time interval of cell reception, a controller for reading out the reception time stored in the data table the controller receiving the timeout detection start signal from the timer, an adder for adding the reception time from the data table and the timeout value stored in the first register means, a comparator for comparing the result of the addition by the adder with the time data from the timer, and a decision circuit for receiving the comparison result from the comparator and deciding whether or not the cell of the frame in the reassembly is a timeout based on the comparison result. In the timeout process circuit, the reception time of the cell is stored in the data table when the cell is received by the receiver.

摘要翻译： 一种用于执行结合在接收机中的超时检测处理的超时处理电路，具有用于递增指示当前时间的时间数据的定时器，包括数据表的存储器，用于存储由接收机最近接收的单元的接收时间， 存储指示小区接收的最大允许时间间隔的超时值;控制器，用于读出存储在数据表中的接收时间，控制器从定时器接收超时检测开始信号;加法器，用于从数据表中添加接收时间 以及存储在第一寄存器装置中的超时值，用于将加法器的相加结果与来自定时器的时间数据进行比较的比较器，以及用于从比较器接收比较结果的判定电路，以及判定单元 在重新组合中的帧是基于比较结果的超时。 在超时处理电路中，当接收器接收到该信元时，该信元的接收时间被存储在数据表中。