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公开(公告)号：USRE38944E1
公开(公告)日：2006-01-24
申请号：US09974962
申请日：2001-10-12
IPC分类号： G11C8/00
CPC分类号： H01L27/10805 , G11C7/10 , G11C11/408 , G11C11/4096 , G11C11/4097 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and columns selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 子存储垫上面是：主字线和列选择信号线与正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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公开(公告)号：US20050073895A1
公开(公告)日：2005-04-07
申请号：US10636558
申请日：2003-08-08
IPC分类号： G11C11/403 , G11C7/00 , G11C11/34 , G11C11/401 , G11C11/406
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
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公开(公告)号：US6107869A
公开(公告)日：2000-08-22
申请号：US96456
申请日：1998-06-11
IPC分类号： G11C11/41 , G11C5/14 , G11C8/08 , G11C11/401 , G11C11/407 , G11C11/409 , H01L21/3205 , H01L21/822 , H01L21/8242 , H01L23/52 , H01L27/04 , H01L27/108 , G05F3/02
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002
摘要： It is possible to reduce the voltage drop on sub-power supply lines for reducing the subthreshold current and thereby prevent the operating speed of a logic circuit from lowering. Main power supply lines are arranged along one side of a rectangular region including a MOS logic circuit whose subthreshold current must be reduced, and a plurality of sub-power supply lines are arranged on the region in the direction perpendicular to the main power supply lines. A plurality of switching MOS transistors for selectively electrically connecting the sub-power supply lines to the main power supply line are dispersedly arranged with respect to the main power supply line. By dispersedly arranging the switching MOS transistors with respect to the main power supply line, it is possible to reduce the equivalent resistance of the sub-power supply lines compared to the case where switching MOS transistors are provided at one place.
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公开(公告)号：US5983358A
公开(公告)日：1999-11-09
申请号：US938962
申请日：1997-09-26
申请人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
发明人： Masashi Horiguchi , Shinichi Miyatake , Tathunori Mushya , Yasuhiro Kasama , Yoichi Matsuno , Yasushi Kawase , Yoshinobu Nakagome
IPC分类号： G11C11/401 , G06F11/00 , G11C29/00 , G11C29/04
CPC分类号： G11C29/842
摘要： A semiconductor memory having a redundancy circuit includes a judgment device for receiving outputs of first ROMs for storing a defective address therein and judging whether or not a defective memory cell and a spare memory cell to replace the defective memory cell belong to the same memory cell, and also includes a timing adjustment circuit for changing the timing of control signals applied to memory mat control circuits according to an output of the judgment device. When the defective and spare memory cells belong to the same memory mat, the timing of the control signals is made fast.
摘要翻译： 具有冗余电路的半导体存储器包括判断装置，用于接收用于存储缺陷地址的第一ROM的输出，并判断有缺陷的存储单元和备用存储单元是否属于同一个存储单元， 并且还包括定时调整电路，用于根据判断装置的输出来改变施加到存储器垫控制电路的控制信号的定时。 当有缺陷的和备用的存储器单元属于相同的存储器存储器时，控制信号的定时变得快。
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公开(公告)号：US5966341A
公开(公告)日：1999-10-12
申请号：US982398
申请日：1997-12-02
IPC分类号： G11C11/401 , G11C7/10 , G11C11/407 , G11C11/408 , G11C11/409 , G11C11/4096 , G11C11/4097 , H01L21/8242 , H01L27/105 , H01L27/108 , G11C13/00
CPC分类号： H01L27/10805 , G11C11/408 , G11C11/4096 , G11C11/4097 , G11C7/10 , H01L27/105
摘要： A semiconductor memory such as a dynamic RAM having memory mats each divided into a plurality of units or sub-memory mats. Each sub-memory mat comprises: a memory array having sub-word lines and sub-bit lines intersecting orthogonally and dynamic memory cells located in lattice fashion at the intersection points between the intersecting sub-word and sub-bit lines; a sub-word line driver including unit sub-word line driving circuits corresponding to the sub-word lines; a sense amplifier including unit amplifier circuits and column selection switches corresponding to the sub-bit lines; and sub-common I/O lines to which designated sub-bit lines are connected selectively via the column selection switches. The sub-memory mats are arranged in lattice fashion. Above the sub-memory mats is a layer of: main word lines and column selection signal lines intersecting orthogonally, the main word lines having a pitch that is an integer multiple of the pitch of the sub-word lines, the column selection signal lines having a pitch that is an integer multiple of the pitch of the sub-bit lines; and main common I/O lines to which designated sub-common I/O lines are connected selectively.
摘要翻译： 具有各自被划分为多个单元或子存储器垫的存储器垫的动态RAM等半导体存储器。 每个子存储器垫包括：存储器阵列，其具有在相交的子字和子位线之间的交叉点处以网格方式位于正交和动态存储器单元的子字线和子位线; 子字线驱动器，包括对应于子字线的单元子字线驱动电路; 感测放大器，包括对应于子位线的单位放大器电路和列选择开关; 以及经由列选择开关选择性地连接指定子位线的子公共I / O线。 子存储垫以格子排列。 在子存储器衬垫之上是与主要字线和列选择信号线正交相交的层，主字线具有作为子字线的间距的整数倍的间距，列选择信号线具有 间距，是子位线的间距的整数倍; 以及选择性地连接指定的子公共I / O线的主要公共I / O线。
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6.发明申请公开(公告)号：US20110012906A1
公开(公告)日：2011-01-20
申请号：US12890642
申请日：2010-09-25
申请人： Yasushi KAWASE , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi KAWASE , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G06F12/02
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。
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7.发明授权公开(公告)号：US07826264B2
公开(公告)日：2010-11-02
申请号：US11441166
申请日：2006-05-26
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设定驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。
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8.发明授权Semiconductor integrated circuit including first and second switching transistors having operation states corresponding to operation states of first and second logic circuits 有权包括具有对应于第一和第二逻辑电路的操作状态的操作状态的第一和第二开关晶体管的半导体集成电路公开(公告)号：US07199648B2
公开(公告)日：2007-04-03
申请号：US10859141
申请日：2004-06-03
IPC分类号： G05F1/10
CPC分类号： G11C8/08 , G11C5/14 , G11C5/147 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor integrated circuit is provided having first and second logic circuits coupled to first and second sub-power supply lines, respectively. First and second switching transistors are also provided to connect the first and second sub-power supply lines to a main power supply line. The first and second switching transistors are kept off in an operation stop state of the first and second logic circuits, and are kept on in operable state of the first and second logic circuits.
摘要翻译： 提供半导体集成电路，其具有分别耦合到第一和第二子电源线的第一和第二逻辑电路。 还提供第一和第二开关晶体管以将第一和第二子电源线连接到主电源线。 第一和第二开关晶体管被保持在第一和第二逻辑电路的操作停止状态，并且保持在第一和第二逻辑电路的可操作状态。
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公开(公告)号：US20060227642A1
公开(公告)日：2006-10-12
申请号：US11448016
申请日：2006-06-07
IPC分类号： G11C7/00
CPC分类号： G11C11/40615 , G11C11/406 , G11C11/408 , G11C2211/4061
摘要： With the objective of providing a semiconductor memory device which is made identical in usability to a static RAM by use of dynamic memory cells and realizes a high-speed memory cycle time, there is provided a pseudo static RAM having a time multiplex mode which, when instructions for a memory operation for reading memory information from each of memory cells each requiring a refresh operation for periodically holding the memory information, or writing the same therein is issued, carries out an addressing-based autonomous refresh operation different from the memory operation before or after the memory operation. The pseudo static RAM includes address signal transition detectors for a row and a column, and a page mode which independently performs a column address selecting operation according to an address signal transition detect signal of the second address signal transition detector.
摘要翻译： 为了提供通过使用动态存储器单元使与静态RAM相同的半导体存储器件的目的，实现高速存储器周期时间，提供了一种具有时间多路复用模式的伪静态RAM，当时 发出用于从每个存储单元读取存储器信息的存储器操作的指令，每个存储器单元需要周期性地保持存储器信息的刷新操作，或者写入其中的存储器信息，执行与之前或之前的存储器操作不同的基于寻址的自主刷新操作， 内存操作后。 伪静态RAM包括用于行和列的地址信号转换检测器，以及根据第二地址信号转换检测器的地址信号转移检测信号独立地执行列地址选择操作的页模式。
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10.发明申请公开(公告)号：US20120069670A1
公开(公告)日：2012-03-22
申请号：US13305532
申请日：2011-11-28
申请人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
发明人： Yasushi Kawase , Susumu Ishida , Takesada Akiba , Yasushi Nagata , Naoki Miyamoto , Kazuyoshi Shiba
IPC分类号： G11C11/34
CPC分类号： G09G3/3655 , G09G5/005 , G09G2310/08 , H01L27/0207 , H01L27/11521 , H01L27/11558 , H01L29/42324 , H01L29/42328 , H01L29/7885
摘要： The present invention realizes a semiconductor integrated circuit device for driving liquid crystal (liquid crystal control driver IC) capable of easily setting drive conditions and the like according to specifications of a liquid crystal display to be used. An electrically-programmable nonvolatile memory circuit (EPROM) or an electrically erasable and programmable nonvolatile memory circuit (EEPROM) is provided in a semiconductor integrated circuit device for driving a liquid crystal display, and setting information is stored in the memory circuit. The memory circuit is constructed by a normal device which can be formed in the same process as a semiconductor manufacturing process of forming devices of other circuits.
摘要翻译： 本发明实现了一种用于驱动液晶（液晶控制驱动器IC）的半导体集成电路器件，其能够根据要使用的液晶显示器的规格容易地设置驱动条件等。 在用于驱动液晶显示器的半导体集成电路器件中提供电可编程非易失性存储器电路（EPROM）或电可擦除和可编程的非易失性存储器电路（EEPROM），并将设置信息存储在存储器电路中。 存储电路由与其他电路的形成器件的半导体制造工艺相同的工艺形成的普通器件构成。
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