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    Electrostatic Discharge Protection Circuit
    1.
    发明申请
    Electrostatic Discharge Protection Circuit 有权
    静电放电保护电路

    公开(公告)号：US20100232078A1

    公开(公告)日：2010-09-16

    申请号：US12438460

    申请日：2007-10-30

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    IPC分类号： H02H9/04

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

    摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

    Electrostatic discharge protection in a semiconductor device
    2.
    发明授权
    Electrostatic discharge protection in a semiconductor device 有权
    半导体器件中的静电放电保护

    公开(公告)号：US07495873B2

    公开(公告)日：2009-02-24

    申请号：US10977881

    申请日：2004-10-29

    申请人： Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    IPC分类号： H02H9/00

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit for protecting a circuit from an ESD event occurring between a first voltage supply node and a second voltage supply node associated with the circuit to be protected includes an MOS device having a gate terminal, a first source/drain terminal and a second source/drain terminal. The first source/drain terminal is connected to the first voltage supply node and the second source/drain terminal is connected to the second voltage supply node. The ESD protection circuit further includes a trigger circuit coupled to the gate terminal of the MOS device. The trigger circuit is configured to generate a control signal at the gate terminal of the MOS device for activating the MOS device during the ESD event. At least a portion of the trigger circuit is formed in a floating well which becomes biased to a voltage that is substantially equal to a first voltage when the first voltage is supplied to the first voltage supply node or to a second voltage when the second voltage is applied to the second voltage supply node, whichever voltage is greater.

    摘要翻译： 一种ESD保护电路，用于保护电路免受在要被保护的电路的第一电压供应节点和第二电压供应节点之间发生的ESD事件的影响，包括具有栅极端子，第一源极/漏极端子和第二电压源的MOS器件 源极/漏极端子。 第一源极/漏极端子连接到第一电压供应节点，第二源极/漏极端子连接到第二电压供应节点。 ESD保护电路还包括耦合到MOS器件的栅极端子的触发电路。 触发电路被配置为在MOS器件的栅极端产生控制信号，以在ESD事件期间激活MOS器件。 触发电路的至少一部分形成在浮置阱中，当浮置第二电压为第二电压时，浮置阱被偏置到基本上等于第一电压的电压，或者当第一电压被提供给第一电压供应节点时， 施加到第二电压供应节点，无论哪个电压较大。

    Semiconductor resistor
    4.
    发明申请
    Semiconductor resistor 有权
    半导体电阻

    公开(公告)号：US20050168319A1

    公开(公告)日：2005-08-04

    申请号：US10768771

    申请日：2004-01-30

    申请人： Dipankar Bhattacharya ,  John Kriz ,  Stefan Siegel ,  Joseph Simko ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  John Kriz ,  Stefan Siegel ,  Joseph Simko ,  Yehuda Smooha

    IPC分类号： H01C1/14 ,  H01L21/02 ,  H01L23/522 ,  H01L27/08 ,  H01C1/012

    CPC分类号： H01L28/20 ,  H01C1/14 ,  H01L23/5228 ,  H01L27/0802 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A semiconductor resistor comprises a resistor body formed on a semiconductor substrate and first and second conductive terminals electrically connected to the resistor body at opposite ends thereof. The semiconductor resistor further includes at least first and second conductive paths between at least one of the first and second conductive terminals and the resistor body. The at least one conductive terminal is configured such that a resistance of the at least one conductive terminal between the at least first and second conductive paths is substantially matched to a resistance of the resistor body between the at least first and second conductive paths. In this manner, a current distribution between the at least first and second conductive paths is substantially matched.

    摘要翻译： 半导体电阻器包括形成在半导体衬底上的电阻体和在其两端电连接到电阻体的第一和第二导电端子。 半导体电阻器还包括在第一和第二导电端子和电阻器主体中的至少一个之间的至少第一和第二导电路径。 至少一个导电端子被配置为使得至少第一和第二导电路径之间的至少一个导电端子的电阻基本上与至少第一和第二导电路径之间的电阻体的电阻相匹配。 以这种方式，至少第一和第二导电路径之间的电流分布基本匹配。

    Method for concurrently forming an ESD protection device and a shallow trench isolation region
    5.
    发明授权
    Method for concurrently forming an ESD protection device and a shallow trench isolation region 有权
    同时形成ESD保护器件和浅沟槽隔离区域的方法

    公开(公告)号：US06503793B1

    公开(公告)日：2003-01-07

    申请号：US09927752

    申请日：2001-08-10

    申请人： Sailesh Chittipeddi ,  Yehuda Smooha

    发明人： Sailesh Chittipeddi ,  Yehuda Smooha

    IPC分类号： H01L218242

    CPC分类号： H01L29/66181 ,  H01L21/76229 ,  H01L21/763 ,  H01L27/0251 ,  H01L29/945

    摘要： The present invention provides a method of forming a trench capacitor in an input/output region and a trench isolation structure in an active device region and a method of manufacturing an integrated circuit using the aforementioned method of forming. The invention comprises concurrently forming an isolation trench in an active region and a capacitive trench in an input/output region, concurrently forming a dielectric layer over the walls of the isolation trench and the capacitive trench, and forming a conductive material in the capacitive trench.

    摘要翻译： 本发明提供一种在有源器件区域中的输入/输出区域和沟槽隔离结构中形成沟槽电容器的方法和使用上述形成方法制造集成电路的方法。 本发明包括在输入/输出区域中的有源区域和电容沟槽中同时形成隔离沟槽，同时在隔离沟槽和电容沟槽的壁上形成电介质层，并在电容沟槽中形成导电材料。

    Electrostatic discharge protection circuit
    7.
    发明授权
    Electrostatic discharge protection circuit 有权
    静电放电保护电路

    公开(公告)号：US08089739B2

    公开(公告)日：2012-01-03

    申请号：US12438460

    申请日：2007-10-30

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    IPC分类号： H02H3/22 ,  H02H3/20 ,  H02H9/04

    CPC分类号： H01L27/0266

    摘要： An ESD protection circuit includes a first voltage clamp, connected between a first voltage supply node and a second voltage supply node of the circuit, and a second voltage clamp, connected between the second voltage supply node and a voltage return of the circuit. The first voltage supply node is adapted to receive a first voltage which is greater than a prescribed gate oxide reliability potential of the circuit. The second voltage supply node is operative to receive a second voltage which is less than the first voltage. The first voltage clamp is operative to clamp the first voltage on the first voltage supply node to a first value during an ESD event between the first and second voltage supply nodes, and the second voltage clamp is operative to clamp the second voltage on the second voltage supply node to a second value during an ESD event between the second voltage supply node and the voltage return.

    摘要翻译： ESD保护电路包括连接在电路的第一电压供应节点和第二电压供应节点之间的第一电压钳位器，以及连接在第二电压供应节点和电路的电压回路之间的第二电压钳位。 第一电压供应节点适于接收大于电路的预定栅极氧化物可靠性电位的第一电压。 第二电压供应节点可操作以接收小于第一电压的第二电压。 第一电压钳位器用于在第一和第二电压供应节点之间的ESD事件期间将第一电压供应节点上的第一电压钳位到第一值，并且第二电压钳位器用于将第二电压钳位在第二电压 在第二电压供应节点和电压返回之间的ESD事件期间将供应节点提供给第二值。

    Self-bypassing voltage level translator circuit
    9.
    发明授权
    Self-bypassing voltage level translator circuit 有权
    自我旁路电压电平转换电路

    公开(公告)号：US07145364B2

    公开(公告)日：2006-12-05

    申请号：US11065785

    申请日：2005-02-25

    申请人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    发明人： Dipankar Bhattacharya ,  Makeshwar Kothandaraman ,  John C. Kriz ,  Bernard L. Morris ,  Yehuda Smooha

    IPC分类号： H03K19/0175

    CPC分类号： H03K3/012 ,  H03K3/356113 ,  H03K17/102

    摘要： A voltage level translator circuit is selectively operable in one of at least two modes in response to a control signal. In a first mode, the voltage level translator circuit is operative to translate an input signal referenced to a first source providing a first voltage to an output signal referenced to a second source providing a second voltage. In a second mode, the voltage level translator circuit is operative to provide a signal path from an input of the voltage translator circuit to an output thereof without translating the input signal. The control signal is indicative of a difference between the first voltage and the second voltage.

    摘要翻译： 响应于控制信号，电压电平转换器电路可选择性地以至少两种模式之一工作。 在第一模式中，电压电平转换器电路用于将提供第一电压的参考第一源的输入信号转换为参考提供第二电压的第二源的输出信号。 在第二模式中，电压电平转换器电路用于提供从电压转换器电路的输入到其输出的信号路径，而不转换输入信号。 控制信号表示第一电压和第二电压之间的差。

    Moderate current 5V tolerant buffer using a 2.5 volt power supply
    10.
    发明授权
    Moderate current 5V tolerant buffer using a 2.5 volt power supply 有权
    使用2.5伏电源的中等电流5V容限缓冲器

    公开(公告)号：US07002372B2

    公开(公告)日：2006-02-21

    申请号：US10759162

    申请日：2004-01-20

    申请人： Carol Ann Huber ,  Bernard Lee Morris ,  Makeshwar Kothandaraman ,  Yehuda Smooha

    发明人： Carol Ann Huber ,  Bernard Lee Morris ,  Makeshwar Kothandaraman ,  Yehuda Smooha

    IPC分类号： H03K19/0175

    CPC分类号： H03K19/018592 ,  H03K19/00315 ,  H03K19/018521

    摘要： A low voltage, 5V tolerant open drain output buffer having moderate current tolerance capabilities is formed with 3.3V technology using a nominal power supply of 2.5V or less. The buffer includes an inverter, a series connection of the current paths of three n-channel FET transistors, and a backgate bias generator. One terminal of the series connection of three transistors is connected to a PAD, and the other terminal of the lower transistor of the series is connected to ground. The bias generator is formed using two p-channel field effect transistors (FETs) that are cross-connected between VDD and the PAD. A gate of a central one of the three transistors is connected to the power supply. An output of the bias generator is connected to a gate of the upper transistor. The inventive buffer may be manufactured using standard 3.3V processes, but functions with a power supply of, e.g., 2.5V or 1.8V.

    摘要翻译： 具有中等电流公差能力的低电压，5V容限开漏输出缓冲器采用3.3V技术，使用2.5V或更小的额定电源。 缓冲器包括反相器，三个n沟道FET晶体管的电流路径的串联连接和背栅偏置发生器。 三个晶体管的串联连接的一个端子连接到PAD，并且该串联的下部晶体管的另一个端子连接到地。 偏置发生器使用在VDD和PAD之间交叉连接的两个p沟道场效应晶体管（FET）形成。 三个晶体管的中心一个的栅极连接到电源。 偏置发生器的输出端连接到上部晶体管的栅极。 本发明的缓冲器可以使用标准的3.3V工艺制造，但是功率为例如2.5V或1.8V的电源。