公开(公告)号：US08207043B2

公开(公告)日：2012-06-26

申请号：US12568657

申请日：2009-09-28

申请人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

发明人： Huang-Yi Lin ,  Jiun-Hung Shen ,  Chi-Horn Pai ,  Yi-Chung Sheng ,  Shih-Chieh Hsu

IPC分类号： H01L21/336

CPC分类号： H01L29/78 ,  H01L21/26506 ,  H01L21/26513 ,  H01L21/268 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/7847

摘要： A method for making a semiconductor MOS device is provided. A gate structure is formed on a substrate. A source and a drain are formed in the substrate on both sides of the gate structure. The substrate is then subjected to a pre-amorphization implant (PAI) process. A transitional stress layer is then formed on the substrate. Thereafter, a laser anneal with a first temperature is performed. After the laser anneal, a rapid thermal process is performed with a second temperature that is lower than the first temperature. Subsequently, the transitional stress layer is removed.

摘要翻译： 提供了制造半导体MOS器件的方法。 在基板上形成栅极结构。 源极和漏极形成在栅极结构两侧的衬底中。 然后将基材进行预非晶化植入（PAI）工艺。 然后在衬底上形成过渡应力层。 此后，进行具有第一温度的激光退火。 在激光退火之后，以低于第一温度的第二温度进行快速热处理。 随后，去除过渡应力层。

公开(公告)号：US07932104B2

公开(公告)日：2011-04-26

申请号：US12468063

申请日：2009-05-19

申请人： Chia-Chen Sun ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh

发明人： Chia-Chen Sun ,  Yi-Chung Sheng ,  Sheng-Yuan Hsueh

IPC分类号： G01R31/26

CPC分类号： H01L22/34 ,  G03F7/70658 ,  H01L22/14

摘要： A method for inspecting a photoresist pattern is disclosed. First, a substrate with a first doping region is provided. Then, a photoresist is formed to cover the substrate. Later, the photoresist is patterned to form a photoresist pattern. Afterwards, the substrate is doped by using the photoresist pattern, and a PN junction exists in the first doping region. Thereafter, a current passing through the PN junction is tested to inspect the photoresist pattern.

摘要翻译： 公开了一种用于检查光致抗蚀剂图案的方法。 首先，提供具有第一掺杂区域的衬底。 然后，形成光致抗蚀剂以覆盖基板。 之后，将光致抗蚀剂图案化以形成光致抗蚀剂图案。 之后，通过使用光致抗蚀剂图案来掺杂衬底，并且PN结存在于第一掺杂区域中。 此后，测试通过PN结的电流，以检查光刻胶图案。

公开(公告)号：US20090137089A1

公开(公告)日：2009-05-28

申请号：US12366625

申请日：2009-02-05

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L21/8238 ,  H01L21/76

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US07342284B2

公开(公告)日：2008-03-11

申请号：US11307660

申请日：2006-02-16

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L29/94

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US5654576A

公开(公告)日：1997-08-05

申请号：US559324

申请日：1995-11-16

申请人： Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

发明人： Chen-Chiu Hsue ,  Yi-Chung Sheng ,  Shing-Ren Sheu ,  Chen-Hui Chung

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L29/94

CPC分类号： H01L27/1126 ,  H01L27/112 ,  Y10S257/915

摘要： A method of manufacturing a code pattern on a semiconductor substrate with an array of substantially parallel buried bit lines integral therewith and with word lines above the buried bit lines, includes: forming a titanium nitride layer above the word lines, forming and patterning a code mask above the titanium nitride layer, implanting impurities into the substrate through openings in the code mask to form the code pattern, and performing rapid thermal annealing of the implant. The step height of the titanium nitride layer is employed to form the code identification on the substrate.

摘要翻译： 一种在半导体衬底上制造具有与其一体的基本上平行的掩埋位线阵列和掩埋位线之上的字线的阵列的方法，包括：在字线之上形成氮化钛层，形成码图掩模 在氮化钛层之上，通过编码掩模中的开口将杂质注入到衬底中，以形成编码图案，并对植入物进行快速热退火。 氮化钛层的台阶高度用于在基板上形成代码识别。

公开(公告)号：US5545580A

公开(公告)日：1996-08-13

申请号：US530746

申请日：1995-09-19

申请人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

发明人： Yi-Chung Sheng ,  Chen-Hui Chung ,  Kuan-Cheng Su

IPC分类号： H01L27/112 ,  H01L21/8246

CPC分类号： H01L27/112

摘要： A multi-state read-only-memory device and a method for fabricating the same is suitable for forming on a semiconductor substrate. The read-only memory device is provided with bit lines and word lines which are mutually intersecting. In accordance with the present invention, multiple polysilicon selective deposition procedures are utilized to form a plurality of protrusion portions onto the word lines but with multiple thicknesses. Then, one implantation procedure is applied to program the device into multiple states at the same time without incurring misalignment problems that result in inaccuracy.

摘要翻译： 多状态只读存储器件及其制造方法适用于在半导体衬底上形成。 只读存储器件具有相互相交的位线和字线。 根据本发明，利用多个多晶硅选择性沉积程序在字线上形成多个突出部分，但具有多个厚度。 然后，应用一个植入程序同时将器件编程成多个状态，而不会导致导致不准确的错位问题。

公开(公告)号：US08278166B2

公开(公告)日：2012-10-02

申请号：US12837519

申请日：2010-07-16

申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹部中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

公开(公告)号：US20120012938A1

公开(公告)日：2012-01-19

申请号：US12837519

申请日：2010-07-16

申请人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

发明人： Chun-Chia Chen ,  Ying-Hung Chou ,  Zen-Jay Tsai ,  Shih-Chieh Hsu ,  Yi-Chung Sheng ,  Chi-Horn Pai

IPC分类号： H01L27/092 ,  H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823814 ,  H01L21/823864 ,  H01L29/7848

摘要： A method of manufacturing a CMOS device includes providing a substrate having a first region and a second region; forming a first gate structure and a second gate structure, each of the gate structures comprising a sacrificial layer and a hard mask layer; forming a patterned first protecting layer covering the first region and a first spacer on sidewalls of the second gate structure; performing an etching process to form first recesses in the substrate; performing a SEG process to form epitaxial silicon layers in each first recess; forming a patterned second protecting layer covering the second region; and performing a dry etching process with the patterned second protecting layer serving as an etching mask to etch back the patterned first protecting layer to form a second spacer on sidewalls of the first gate structure and to thin down the hard mask layer on the first gate structure.

摘要翻译： 制造CMOS器件的方法包括提供具有第一区域和第二区域的衬底; 形成第一栅极结构和第二栅极结构，每个栅极结构包括牺牲层和硬掩模层; 形成覆盖所述第一区域的图案化的第一保护层和在所述第二栅极结构的侧壁上的第一间隔物; 进行蚀刻工艺以在基板中形成第一凹部; 执行SEG工艺以在每个第一凹槽中形成外延硅层; 形成覆盖所述第二区域的图案化的第二保护层; 以及利用所述图案化的第二保护层作为蚀刻掩模进行干蚀刻工艺，以蚀刻所述图案化的第一保护层，以在所述第一栅极结构的侧壁上形成第二间隔物，并且使所述第一栅极结构上的所述硬掩模层变薄 。

公开(公告)号：US07749833B2

公开(公告)日：2010-07-06

申请号：US12366625

申请日：2009-02-05

申请人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

发明人： Shyh-Fann Ting ,  Cheng-Tung Huang ,  Wen-Han Hung ,  Tzyy-Ming Cheng ,  Tzer-Min Shen ,  Yi-Chung Sheng

IPC分类号： H01L21/8238

CPC分类号： H01L21/823807 ,  H01L21/823864 ,  H01L21/823878 ,  H01L29/165 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7843

摘要： A method of manufacturing a metal-oxide-semiconductor (MOS) transistor device is disclosed. A gate dielectric layer is formed on an active area of a substrate. A gate electrode is patterned on the gate dielectric layer. The gate electrode has vertical sidewalls and a top surface. A liner is formed on the vertical sidewalls of the gate electrode. A nitride spacer is formed on the liner. An ion implanted is performed to form a source/drain region. After salicide process, an STI region that isolates the active area is recessed, thereby forming a step height at interface between the active area and the STI region. The nitride spacer is removed. A nitride cap layer that borders the liner is deposited. The nitride cap layer has a specific stress status.

摘要翻译： 公开了一种制造金属氧化物半导体（MOS）晶体管器件的方法。 栅介质层形成在衬底的有源区上。 在栅极电介质层上形成栅电极。 栅电极具有垂直侧壁和顶表面。 衬套形成在栅电极的垂直侧壁上。 在衬套上形成氮化物间隔物。 进行离子注入以形成源极/漏极区域。 在自对准处理之后，隔离有源区域的STI区域凹陷，从而在有源区域和STI区域之间的界面处形成台阶高度。 去除氮化物间隔物。 与衬垫相邻的氮化物覆盖层被沉积。 氮化物盖层具有特定的应力状态。

公开(公告)号：US5846865A

公开(公告)日：1998-12-08

申请号：US745468

申请日：1996-11-12

申请人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

发明人： Yi-Chung Sheng ,  Cheng-Hui Chung ,  Jih-Wen Chou

IPC分类号： H01L21/8246 ,  H01L27/112 ,  H01L21/8236

CPC分类号： H01L27/11253 ,  H01L27/112 ,  Y10S148/02

摘要： A method of fabricating flat-cell mask ROM devices having buried bit-lines that will not be subject to punch-through between neighboring bit lines as a result of heating in subsequent steps after the buried bit-lines are formed. In the method, the first step is to prepare a semiconductor substrate with a gate oxide layer formed thereon. Thereafter, a first polysilicon layer is formed over the gate oxide layer, and a plurality of trenches at predetermined positions, with these trenches extending through the gate oxide and first polysilicon layer and into the substrate to a predetermined depth. Then, trenches are filled with tungsten to form a plurality of source/drain regions. A second polysilicon layer is then formed over the first polysilicon layer, and an insulating layers is formed over each of the source/drain regions. Thereafter, a third polysilicon layer is formed over the second polysilicon layer and the insulating layers, and finally the third polysilicon layer is defined to form a gate for the integrated circuit device. Since the source/drain regions are made of tungsten metal, the spacing distance therebetween will not be changed when subjected to high-temperature conditions during subsequent process steps. The punch-through effect can thus be avoided.

摘要翻译： 一种制造平面单元掩膜ROM器件的方法，其具有在形成掩埋位线之后的随后步骤中加热的结果之后不会在相邻位线之间穿透的掩埋位线。 在该方法中，第一步是制备其上形成有栅氧化层的半导体衬底。 此后，在栅极氧化物层上形成第一多晶硅层，并在预定位置形成多个沟槽，其中这些沟槽延伸穿过栅极氧化物和第一多晶硅层并进入衬底至预定深度。 然后，用钨填充沟槽以形成多个源极/漏极区域。 然后在第一多晶硅层上形成第二多晶硅层，并且在每个源/漏区上形成绝缘层。 此后，在第二多晶硅层和绝缘层上形成第三多晶硅层，最后形成第三多晶硅层以形成用于集成电路器件的栅极。 由于源极/漏极区域由钨金属制成，因此在后续工艺步骤中经受高温条件时，它们之间的间隔距离将不会改变。 因此可以避免穿透效果。