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    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME
    3.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING THE SAME 审中-公开
    半导体器件及其制造方法

    公开(公告)号：US20130134600A1

    公开(公告)日：2013-05-30

    申请号：US13305593

    申请日：2011-11-28

    Applicant: Chih-Jing Hsu ,  Ying-Te Ou

    Inventor： Chih-Jing Hsu ,  Ying-Te Ou

    IPC: H01L23/48 ,  H01L21/768

    CPC classification number: H01L23/481 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/147 ,  H01L23/15 ,  H01L23/49827 ,  H01L2924/0002 ,  H01L2924/00

    Abstract: The present invention relates to a semiconductor device and method for manufacturing the same. The semiconductor device includes a substrate, a dielectric layer, a metal layer, an interconnection metal and an insulation circular layer. The substrate has at least one through hole. The dielectric layer is disposed adjacent to the substrate. The metal layer is disposed adjacent to the dielectric layer. The interconnection metal is disposed in the at least one through hole. An insulation circular layer surrounds the interconnection metal, wherein the insulation layer has an upper surface and the upper surface contacts the dielectric layer. Whereby, the metal layer can be electrically connected to another surface of the substrate through the interconnection metal.

    Abstract translation: 半导体器件及其制造方法技术领域本发明涉及半导体器件及其制造方法。 半导体器件包括衬底，电介质层，金属层，互连金属和绝缘圆形层。 基板具有至少一个通孔。 电介质层与衬底相邻设置。 金属层设置成与电介质层相邻。 互连金属设置在至少一个通孔中。 绝缘圆形层围绕互连金属，其中绝缘层具有上表面，并且上表面接触电介质层。 由此，金属层可以通过互连金属电连接到衬底的另一表面。

    PACKAGE STRUCTURE WITH EMBEDDED CAPACITOR, FABRICATING PROCESS THEREOF AND APPLICATIONS OF THE SAME
    7.
    发明申请
    PACKAGE STRUCTURE WITH EMBEDDED CAPACITOR, FABRICATING PROCESS THEREOF AND APPLICATIONS OF THE SAME 审中-公开
    嵌入式电容器的封装结构及其制造工艺及其应用

    公开(公告)号：US20080180878A1

    公开(公告)日：2008-07-31

    申请号：US11942487

    申请日：2007-11-19

    Applicant: Yung-Hui Wang ,  Ying-Te Ou ,  Chih-Pin Hung

    Inventor： Yung-Hui Wang ,  Ying-Te Ou ,  Chih-Pin Hung

    IPC: H01L21/283 ,  H01G4/228

    CPC classification number: H01G4/228 ,  H01L23/49822 ,  H01L23/49833 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2924/00014 ,  H01L2924/19041 ,  H05K1/162 ,  H05K3/4611 ,  H05K2201/09981 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

    Abstract: A package structure with an embedded capacitor, a fabricating process thereof and applications of the same are provided, wherein the package structure includes a dielectric layer, a first conductive layer, a second conductive layer, a first embedded plate and a second embedded plate. The dielectric layer has a thickness. The first conductive layer with a first potential is located on one side of the dielectric layer. The second conductive layer with a second potential is located on the dielectric layer at the other side thereof opposite to the first conductive layer. The first embedded plate and the second embedded plate that are embedded in the dielectric layer are separated at a distance, wherein the first embedded plate is electrically connected with the first conductive layer, and the second embedded plate is electrically connected with the second conductive layer.

    Abstract translation: 提供具有嵌入式电容器的封装结构及其制造方法及其应用，其中封装结构包括电介质层，第一导电层，第二导电层，第一嵌入板和第二嵌入板。 电介质层具有厚度。 具有第一电位的第一导电层位于电介质层的一侧。 具有第二电位的第二导电层位于与第一导电层相对的另一侧的电介质层上。 嵌入在电介质层中的第一嵌入板和第二嵌入板被隔开一段距离，其中第一嵌入板与第一导电层电连接，第二嵌入板与第二导电层电连接。

    SUBSTRATE WITH EMBEDDED PASSIVE ELEMENT AND METHODS FOR MANUFACTURING THE SAME
    8.
    发明申请
    SUBSTRATE WITH EMBEDDED PASSIVE ELEMENT AND METHODS FOR MANUFACTURING THE SAME 审中-公开
    具有嵌入式被动元件的基板及其制造方法

    公开(公告)号：US20080164562A1

    公开(公告)日：2008-07-10

    申请号：US11939797

    申请日：2007-11-14

    Applicant: Yung-Hui Wang ,  Ying-Te Ou ,  Chih-Pin Hung

    Inventor： Yung-Hui Wang ,  Ying-Te Ou ,  Chih-Pin Hung

    IPC: H01L21/441 ,  H01L29/92

    CPC classification number: H05K1/162 ,  H01L23/49822 ,  H01L23/50 ,  H01L2924/0002 ,  H05K3/107 ,  H05K3/4644 ,  H05K3/4652 ,  H05K2201/09236 ,  H01L2924/00

    Abstract: A substrate with an embedded passive element and methods for manufacturing the same are provided, wherein the substrate includes an interlayer circuit board having a first conductive circuit, a dielectric layer, a first electrode, a second electrode, and a second conductive circuit. The dielectric layer formed on the interlayer circuit board has a first recess and a second recess for respectively accommodating the first electrode and the second electrode. The embedded passive element is formed by the first electrode, the second electrode, and the dielectric layer between the first electrode and the second electrode. The second conductive circuit electrically connects the first electrode and the second electrode.

    Abstract translation: 提供了具有嵌入式无源元件的基板及其制造方法，其中，基板包括具有第一导电电路，电介质层，第一电极，第二电极和第二导电电路的层间电路板。 形成在层间电路板上的电介质层具有分别容纳第一电极和第二电极的第一凹部和第二凹部。 嵌入式无源元件由第一电极，第二电极和第一电极和第二电极之间的电介质层形成。 第二导电电路将第一电极和第二电极电连接。

    Package structure with embedded die and method of fabricating the same
    9.
    发明授权
    Package structure with embedded die and method of fabricating the same 有权
    具有嵌入式芯片的封装结构及其制造方法

    公开(公告)号：US08120148B2

    公开(公告)日：2012-02-21

    申请号：US12143183

    申请日：2008-06-20

    Applicant: Kuo-Hua Chen ,  Ying-Te Ou ,  Chieh-Chen Fu

    Inventor： Kuo-Hua Chen ,  Ying-Te Ou ,  Chieh-Chen Fu

    IPC: H01L23/495

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L24/16 ,  H01L24/19 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3511

    Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

    Abstract translation: 具有嵌入式管芯的封装结构包括芯层，第一堆积布线结构和第二堆积布线结构。 芯层具有与其相对的第一表面和第二表面。 此外，芯层包括第一介电层，引线框，管芯，第一信号层和第二信号层。 芯片设置在引线框架上并与引线框架电连接。 裸片和引线框架嵌入在第一电介质层中。 第一信号层设置在第一电介质层的上表面上并电连接到引线框架。 第二信号层设置在第一电介质层的底表面上并电连接到引线框。 第一和第二堆积布线结构分别设置在芯层的第一和第二表面上。

    PACKAGE STRUCTURE WITH EMBEDDED DIE AND METHOD OF FABRICATING THE SAME
    10.
    发明申请
    PACKAGE STRUCTURE WITH EMBEDDED DIE AND METHOD OF FABRICATING THE SAME 有权
    嵌入式DIE的包装结构及其制造方法

    公开(公告)号：US20090224378A1

    公开(公告)日：2009-09-10

    申请号：US12143183

    申请日：2008-06-20

    Applicant: KUO-HUA CHEN ,  Ying-Te Ou ,  Chieh-Chen Fu

    Inventor： KUO-HUA CHEN ,  Ying-Te Ou ,  Chieh-Chen Fu

    IPC: H01L23/495 ,  H01L21/60

    CPC classification number: H01L23/5389 ,  H01L21/486 ,  H01L21/56 ,  H01L24/16 ,  H01L24/19 ,  H01L2224/16 ,  H01L2224/16227 ,  H01L2224/18 ,  H01L2924/01006 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/15311 ,  H01L2924/3511

    Abstract: A package structure with an embedded die includes a core layer, a first build-up wiring structure, and a second build-up wiring structure. The core layer has a first surface and a second surface opposite thereto. Besides, the core layer includes a first dielectric layer, a leadframe, a die, a first signal layer, and a second signal layer. The die is disposed on and electrically connected to the leadframe. The die and the leadframe are embedded in the first dielectric layer. The first signal layer is disposed on an upper surface of the first dielectric layer and electrically connected to the leadframe. The second signal layer is disposed on a bottom surface of the first dielectric layer and electrically connected to the leadframe. The first and the second build-up wiring structures are disposed on the first and the second surfaces of the core layer, respectively.

    Abstract translation: 具有嵌入式管芯的封装结构包括芯层，第一堆积布线结构和第二堆积布线结构。 芯层具有与其相对的第一表面和第二表面。 此外，芯层包括第一介电层，引线框，管芯，第一信号层和第二信号层。 芯片设置在引线框架上并与引线框架电连接。 裸片和引线框架嵌入在第一电介质层中。 第一信号层设置在第一电介质层的上表面上并电连接到引线框架。 第二信号层设置在第一电介质层的底表面上并电连接到引线框。 第一和第二堆积布线结构分别设置在芯层的第一和第二表面上。

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