公开(公告)号：US08680538B2

公开(公告)日：2014-03-25

申请号：US12867061

申请日：2008-02-12

申请人： Yoichiro Tarui ,  Kenichi Ohtsuka ,  Naruhisa Miura ,  Yoshinori Matsuno ,  Masayuki Imaizumi

发明人： Yoichiro Tarui ,  Kenichi Ohtsuka ,  Naruhisa Miura ,  Yoshinori Matsuno ,  Masayuki Imaizumi

IPC分类号： H01L29/15

CPC分类号： H01L29/66068 ,  H01L23/3171 ,  H01L23/3192 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/0638 ,  H01L29/0661 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/7811 ,  H01L29/8611 ,  H01L29/8613 ,  H01L29/872 ,  H01L2924/0002 ,  H01L2924/13055 ,  H01L2924/13091 ,  H01L2924/00

摘要： In order to obtain a silicon carbide semiconductor device that ensures both stability of withstand voltage and reliability in high-temperature operations in its termination end-portion provided for electric-field relaxation in the perimeter of a cell portion driven as a semiconductor element, the termination end-portion is provided with an inorganic protection film having high heat resistance that is formed on an exposed surface of a well region as a first region formed on a side of the cell portion, and an organic protection film having a high electrical insulation capability with a little influence by electric charges that is formed on a surface of an electric-field relaxation region formed in contact relation to an outer lateral surface of the well region and apart from the cell portion, and on an exposed surface of the silicon carbide layer.

摘要翻译： 为了获得在作为半导体元件驱动的单元部分的周边中提供用于电场弛豫的其终端部分中的高温操作中的耐受电压的稳定性和可靠性的确保的碳化硅半导体器件， 端部设有具有高耐热性的无机保护膜，所述无机保护膜形成在作为形成在电池单元侧的第一区域的阱区的暴露表面上，以及具有高电绝缘能力的有机保护膜， 在形成于与阱区的外侧表面形成并且与电池部分隔开的电场弛豫区域的表面上以及在碳化硅层的暴露表面上的电荷的一点影响。

公开(公告)号：US20130026494A1

公开(公告)日：2013-01-31

申请号：US13417755

申请日：2012-03-12

申请人： Yasunori ORITSUKI ,  Naoki Yutani ,  Yoichiro Tarui

发明人： Yasunori ORITSUKI ,  Naoki Yutani ,  Yoichiro Tarui

IPC分类号： H01L29/24

CPC分类号： H01L29/7811 ,  H01L29/0615 ,  H01L29/1608 ,  H01L29/402 ,  H01L29/456 ,  H01L29/66068 ,  H01L29/7803 ,  H01L2924/0002 ,  H01L2924/00

摘要： An SiC semiconductor device includes a semiconductor element formed in an SiC substrate, a source electrode and a gate pad formed by using an interconnect layer having barrier metal provided at the bottom surface thereof, and a temperature measuring resistive element formed by using part of the barrier metal in the interconnect line.

摘要翻译： SiC半导体器件包括形成在SiC衬底中的半导体元件，源电极和通过使用其底表面上具有阻挡金属的互连层形成的栅极焊盘，以及通过使用部分势垒形成的温度测量电阻元件 金属在互连线。

公开(公告)号：US08350353B2

公开(公告)日：2013-01-08

申请号：US13037043

申请日：2011-02-28

申请人： Yoichiro Tarui

发明人： Yoichiro Tarui

IPC分类号： H01L23/58

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.

摘要翻译： 提供了一种制造碳化硅半导体器件的方法，其包括以下步骤：在第一导电类型的碳化硅晶片的表面上形成具有第二导电类型的第一区域，其具有通过离子注入铝作为第一杂质的第二导电类型的第一区域 和硼作为第二杂质; 通过激活退火处理将从第一区域注入的硼离子扩散到其相邻区域，从第一区域在碳化硅晶片的表面形成JTE区域的步骤; 在第一区域内的空间和第一区域的内部在碳化硅晶片的表面上形成第一电极的步骤; 以及在所述碳化硅晶片的相对表面上形成第二电极的步骤。 因此，可以形成具有宽范围的杂质浓度和期望的击穿电压的JTE区域，而不增加制造工艺的步骤数量。

公开(公告)号：US08084278B2

公开(公告)日：2011-12-27

申请号：US12961868

申请日：2010-12-07

申请人： Yukio Uda ,  Koichi Sekiya ,  Kazuo Kobayashi ,  Yoichiro Tarui

发明人： Yukio Uda ,  Koichi Sekiya ,  Kazuo Kobayashi ,  Yoichiro Tarui

IPC分类号： H01L21/31

CPC分类号： H01L29/7802 ,  C23C16/325 ,  C23C16/56 ,  H01L21/046 ,  H01L22/12 ,  H01L29/0657 ,  H01L29/1608 ,  H01L29/66068 ,  Y10S438/931

摘要： A wafer WF is mounted in a substrate holder, and the substrate holder is placed in a film forming furnace. The film forming furnace is evacuated by a vacuum pump through a gas discharge part to remove remaining oxygen as completely as possible. Then, a temperature in the film forming furnace is heated to a range of 800° C. to 950° C. under reduced pressure while an inert gas such as Ar or helium (He) is being introduced through a gas introduction part. When the temperature reaches this temperature range, an inflow of the inert gas is stopped. Vaporized ethanol is introduced as a source gas into the film forming furnace through the gas introduction part, thus forming a graphite film on an entire surface of the wafer WF.

摘要翻译： 将晶片WF安装在基板保持器中，并将基板保持器放置在成膜炉中。 成膜炉通过真空泵通过气体排出部分排出，以尽可能完全地除去剩余的氧气。 然后，将成膜炉中的温度在减压下加热至800℃至950℃的范围，同时通过气体引入部分引入诸如Ar或氦（He）的惰性气体。 当温度达到该温度范围时，停止惰性气体的流入。 通过气体导入部将蒸发的乙醇作为原料气体引入成膜炉，从而在晶片WF的整个表面上形成石墨膜。

公开(公告)号：US20100291762A1

公开(公告)日：2010-11-18

申请号：US12627403

申请日：2009-11-30

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L21/265

CPC分类号： H01L29/872 ,  H01L21/046 ,  H01L29/0615 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/6606 ,  H01L29/66068 ,  H01L29/7811 ,  H01L29/8611 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method of manufacturing a silicon carbide semiconductor device is provided that includes a step of forming in a surface of a silicon carbide wafer of first conductivity type a first region of second conductivity type having a predetermined space thereinside by ion-implanting aluminum as a first impurity and boron as a second impurity; a step of forming a JTE region in the surface of the silicon carbide wafer from the first region by diffusing the boron ion-implanted in the first region toward its neighboring zones by an activation annealing treatment; a step of forming a first electrode on the surface of the silicon carbide wafer at the space inside the first region and at an inner part of the first region; and a step of forming a second electrode on the opposite surface of the silicon carbide wafer. Thereby, a JTE region can be formed that has a wide range of impurity concentration and a desired breakdown voltage without increasing the number of steps of the manufacturing process.

摘要翻译： 提供了一种制造碳化硅半导体器件的方法，其包括以下步骤：在第一导电类型的碳化硅晶片的表面上形成第二导电类型的第一区域，其具有通过离子注入铝作为第一杂质而具有其内部的预定空间 和硼作为第二杂质; 通过激活退火处理将从第一区域注入的硼离子扩散到其相邻区域，从第一区域在碳化硅晶片的表面形成JTE区域的步骤; 在第一区域内的空间和第一区域的内部在碳化硅晶片的表面上形成第一电极的步骤; 以及在所述碳化硅晶片的相对表面上形成第二电极的步骤。 因此，可以形成具有宽范围的杂质浓度和期望的击穿电压的JTE区域，而不增加制造工艺的步骤数量。

公开(公告)号：US07564072B2

公开(公告)日：2009-07-21

申请号：US11142322

申请日：2005-06-02

申请人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

发明人： Kenichi Ohtsuka ,  Yoichiro Tarui ,  Yoshinori Matsuno ,  Kenichi Kuroda ,  Hiroshi Sugimoto

IPC分类号： H01L29/74

CPC分类号： H01L29/0619 ,  H01L29/1608 ,  H01L29/872 ,  Y10S388/917

摘要： A semiconductor device includes an anode electrode in Schottky contact with an n-type drift layer formed in an SiC substrate and a JTE region formed outside the anode electrode. The JTE region is made up of a first p-type zone formed in an upper portion of the drift layer under an edge of the anode electrode and a second p-type zone formed outside the first p-type zone having a lower surface impurity concentration than the first p-type zone. The second p-type zone is provided 15 μm or more outwardly away from the edge of the anode electrode. The surface impurity concentration of the first p-type zone ranges from 1.8×1013 to 4×1013 cm−2, and that of the second p-type zone ranges from 1×1013 to 2.5×1013 cm−2.

摘要翻译： 半导体器件包括与形成在SiC衬底中的n型漂移层肖特基接触的阳极电极和形成在阳极电极外部的JTE区域。 JTE区域由在阳极电极的边缘的漂移层的上部形成的第一p型区域和形成在具有较低表面杂质浓度的第一p型区域外的第二p型区域构成 比第一个p型区域。 第二个p型区域距离阳极电极的边缘向外提供15个或更多个外部。 第一p型区域的表面杂质浓度范围为1.8×1013〜4×1013cm-2，第二p型区域的表面杂质浓度为1×10 13〜2.5×10 13 cm -2。

公开(公告)号：US20060134847A1

公开(公告)日：2006-06-22

申请号：US11353992

申请日：2006-02-15

申请人： Yoichiro Tarui ,  Ken-ichi Ohtsuka ,  Masayuki Imaizumi ,  Hiroshi Sugimoto ,  Tetsuya Takami

发明人： Yoichiro Tarui ,  Ken-ichi Ohtsuka ,  Masayuki Imaizumi ,  Hiroshi Sugimoto ,  Tetsuya Takami

IPC分类号： H01L21/8238 ,  H01L21/336 ,  H01L21/265

CPC分类号： H01L29/7802 ,  H01L21/0465 ,  H01L21/047 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/66068

摘要： A semiconductor device and its manufacturing method are provided in which the trade-off relation between channel resistance and JFET resistance, an obstacle to device miniaturization, is improved and the same mask is used to form a source region and a base region by ion implantation. In a vertical MOSFET that uses SiC, a source region and a base region are formed by ion implantation using the same tapered mask to give the base region a tapered shape. The taper angle of the tapered mask is set to 30° to 60° when the material of the tapered mask has the same range as SiC in ion implantation, and to 20° to 45° when the material of the tapered mask is SiO2.

摘要翻译： 提供了一种半导体器件及其制造方法，其中改善了沟道电阻和JFET电阻之间的折衷关系，从而改善了器件的小型化，并且通过离子注入使用相同的掩模形成源极区域和基极区域。 在使用SiC的垂直MOSFET中，通过使用相同的锥形掩模的离子注入形成源极区域和基极区域，以使基极区域呈锥形。 当锥形掩模的材料与离子注入中的SiC具有相同的范围时，锥形掩模的锥角设定为30°至60°，当锥形掩模的材料为SiO 2 。

公开(公告)号：US08685848B2

公开(公告)日：2014-04-01

申请号：US13355710

申请日：2012-01-23

申请人： Yoshinori Matsuno ,  Yoichiro Tarui

发明人： Yoshinori Matsuno ,  Yoichiro Tarui

IPC分类号： H01L21/329

CPC分类号： H01L29/1608 ,  H01L21/0465 ,  H01L21/0485 ,  H01L29/0615 ,  H01L29/0619 ,  H01L29/6606 ,  H01L29/872

摘要： A silicon oxide film is formed on an epitaxial layer by dry thermal oxidation, an ohmic electrode is formed on a back surface of a SiC substrate, an ohmic junction is formed between the ohmic electrode and the back surface of the SiC substrate by annealing the SiC substrate, the silicon oxide film is removed, and a Schottky electrode is formed on the epitaxial layer. Then, a sintering treatment is performed to form a Schottky junction between the Schottky electrode and the epitaxial layer.

摘要翻译： 通过干热氧化在外延层上形成氧化硅膜，在SiC衬底的背面上形成欧姆电极，在SiC衬底的欧姆电极和背面之间形成欧姆接头，退火SiC 衬底，除去氧化硅膜，在外延层上形成肖特基电极。 然后，进行烧结处理以在肖特基电极和外延层之间形成肖特基结。

公开(公告)号：US08115211B2

公开(公告)日：2012-02-14

申请号：US12621963

申请日：2009-11-19

申请人： Yoichiro Tarui

发明人： Yoichiro Tarui

IPC分类号： H01L31/0312 ,  H01L31/0256 ,  H01L29/74 ,  H01L29/76 ,  H01L29/94

CPC分类号： H01L21/0455 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/66068

摘要： An objective is to provide a manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the manufacturing method increase of the manufacturing cost can also be prevented as much as possible. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch

摘要翻译： 目的是提供一种碳化硅半导体器件的制造方法，其中施加到栅极氧化膜的电场可以被放宽，从而可以确保可靠性，并且通过制造方法也可以防止制造成本的增加，因为 尽可能的 形成阱区域，沟道区域和栅电极，使得相对于源极区域的内侧的阱区域，沟道区域和栅极电极的延伸长度为Lwell，Lch和 Lg分别满足Lch

公开(公告)号：US20110244643A1

公开(公告)日：2011-10-06

申请号：US13164430

申请日：2011-06-20

申请人： Yoichiro TARUI

发明人： Yoichiro TARUI

IPC分类号： H01L21/336

CPC分类号： H01L21/0455 ,  H01L29/1095 ,  H01L29/1608 ,  H01L29/42372 ,  H01L29/66068

摘要： A manufacturing method of a silicon carbide semiconductor device in which an electric field applied to a gate oxide film can be relaxed and thereby reliability can be ensured, and by the method manufacturing costs can be reduced. Well regions, channel regions, and gate electrodes are formed so that, given that extending lengths, with respect to the inner sides of source regions, of each of the well regions, the channel regions, and the gate electrodes are Lwell, Lch, and Lg, respectively, a relationship of Lch

摘要翻译： 可以缓和施加到栅极氧化膜的电场的碳化硅半导体器件的制造方法，从而可以确保可靠性，并且通过该方法可以降低制造成本。 形成阱区域，沟道区域和栅电极，使得相对于源极区域的内侧的阱区域，沟道区域和栅极电极的延伸长度为Lwell，Lch和 Lg分别满足Lch