公开(公告)号：US09997538B2

公开(公告)日：2018-06-12

申请号：US15585211

申请日：2017-05-03

申请人： Yong Hoon Son ,  Yoon Jae Kim ,  Seok Woo Nam

发明人： Yong Hoon Son ,  Yoon Jae Kim ,  Seok Woo Nam

IPC分类号： H01L27/115 ,  H01L27/11582

CPC分类号： H01L27/11582 ,  H01L27/11565

摘要： A semiconductor device includes a stacked structure disposed on a semiconductor substrate. The stacked structure includes interlayer insulating layers and gate electrodes, alternately stacked. Separation patterns are disposed to penetrate the stacked structure. A channel structure is disposed between the separation patterns. The channel structure includes a horizontal portion interposed between the stacked structure and the semiconductor substrate while being in contact with the semiconductor substrate and includes vertical portions extending from the horizontal portion in a vertical direction and penetrating the stacked structure. A lower structure is interposed between the horizontal portion and the separation patterns. A dielectric structure is interposed between the vertical portions and the stacked structure and extends between the horizontal portion and the stacked structure.

公开(公告)号：US20170062471A1

公开(公告)日：2017-03-02

申请号：US15249389

申请日：2016-08-27

申请人： Yong-Hoon SON ,  JIN-I LEE ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  JongHeun LIM ,  Wonbong Jung

发明人： Yong-Hoon SON ,  JIN-I LEE ,  Kyunghyun KIM ,  Byeongju KIM ,  Phil Ouk NAM ,  Kwangchul PARK ,  Yeon-Sil SOHN ,  JongHeun LIM ,  Wonbong Jung

IPC分类号： H01L27/115 ,  H01L29/423 ,  H01L29/40 ,  H01L29/792 ,  H01L29/66

CPC分类号： H01L27/11582 ,  H01L27/1157 ,  H01L29/408 ,  H01L29/4234 ,  H01L29/66833 ,  H01L29/7926

摘要： A semiconductor memory device is disclosed. The device may include a stack including gate electrodes stacked on a substrate in a vertical direction and insulating patterns interposed between the gate electrodes, vertical channels passing through the stack and connected to the substrate, a tunnel insulating layer enclosing each of the vertical channels, charge storing patterns provided between the tunnel insulating layer and the gate electrodes and spaced apart from each other in the vertical direction, blocking insulating patterns provided between the charge storing patterns and the gate electrodes and spaced apart from each other in the vertical direction, and a bit line crossing the stack and connected to the vertical channels. The blocking insulating patterns may have a vertical thickness that is greater than that of the gate electrodes.

摘要翻译： 公开了一种半导体存储器件。 该装置可以包括堆叠，其包括沿垂直方向堆叠在基板上的栅电极和插入在栅电极之间的绝缘图案，穿过堆叠并连接到基板的垂直沟道，围绕每个垂直沟道的隧道绝缘层，电荷 存储设置在隧道绝缘层和栅电极之间并在垂直方向上彼此间隔开的图案，阻止在电荷存储图案和栅电极之间设置并且在垂直方向上彼此间隔开的绝缘图案，以及位 线穿过堆叠并连接到垂直通道。 阻挡绝缘图案可以具有大于栅极电极的垂直厚度。

公开(公告)号：US08592873B2

公开(公告)日：2013-11-26

申请号：US13167858

申请日：2011-06-24

申请人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

发明人： Jung Ho Kim ,  Daehyun Jang ,  Myoungbum Lee ,  Kihyun Hwang ,  Sangryol Yang ,  Yong-Hoon Son ,  Ju-Eun Kim ,  Sunghae Lee ,  Dongwoo Kim ,  JinGyun Kim

IPC分类号： H01L29/76

CPC分类号： H01L27/11582 ,  H01L21/02675 ,  H01L21/30604 ,  H01L21/324 ,  H01L27/11551 ,  H01L27/11578 ,  H01L29/7926

摘要： Semiconductor devices and methods of forming the same may be provided. The semiconductor devices may include gate patterns and insulation patterns repeatedly and alternatingly stacked on a substrate. The semiconductor devices may also include a through region penetrating the gate patterns and the insulation patterns. The semiconductor devices may further include a channel structure extending from the substrate through the through region. The channel structure may include a first channel pattern having a first shape. The first channel pattern may include a first semiconductor region on a sidewall of a portion of the through region, and a buried pattern dividing the first semiconductor region. The channel structure may also include a second channel pattern having a second shape. The second channel pattern may include a second semiconductor region in the through region. A grain size of the second semiconductor region may be larger than that of the first semiconductor region.

摘要翻译： 可以提供半导体器件及其形成方法。 半导体器件可以包括在衬底上重复并交替堆叠的栅极图案和绝缘图案。 半导体器件还可以包括穿透栅极图案和绝缘图案的穿透区域。 半导体器件还可以包括从衬底延伸穿过区域的沟道结构。 通道结构可以包括具有第一形状的第一通道图案。 第一沟道图案可以包括贯通区域的一部分的侧壁上的第一半导体区域和分割第一半导体区域的掩埋图案。 通道结构还可以包括具有第二形状的第二通道图案。 第二沟道图案可以包括通孔区域中的第二半导体区域。 第二半导体区域的晶粒尺寸可以大于第一半导体区域的晶粒尺寸。

公开(公告)号：US08482049B2

公开(公告)日：2013-07-09

申请号：US12968389

申请日：2010-12-15

申请人： Yong-Hoon Son ,  Seungjae Baik ,  Jaehun Jeong ,  Kihun Hwang

发明人： Yong-Hoon Son ,  Seungjae Baik ,  Jaehun Jeong ,  Kihun Hwang

IPC分类号： H01L29/76

CPC分类号： G11C16/0483 ,  H01L21/28282 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/66666 ,  H01L29/7827 ,  H01L29/7926

摘要： In semiconductor devices and methods of manufacture, a semiconductor device comprises a substrate of semiconductor material extending in a horizontal direction. A plurality of interlayer dielectric layers are on the substrate. A plurality of gate patterns are provided, each gate pattern between a neighboring lower interlayer dielectric layer and a neighboring upper interlayer dielectric layer. A vertical channel of semiconductor material is on the substrate and extending in a vertical direction through the plurality of interlayer dielectric layers and the plurality of gate patterns. The vertical channel has an outer sidewall, the outer sidewall having a plurality of channel recesses, each channel recess corresponding to a gate pattern of the plurality of gate patterns. The vertical channel has an inner sidewall. An information storage layer is present in the recess between each gate pattern and the vertical channel that insulates the gate pattern from the vertical channel.

摘要翻译： 在半导体器件和制造方法中，半导体器件包括在水平方向上延伸的半导体材料的衬底。 多个层间电介质层位于基板上。 提供多个栅极图案，每个栅极图案在相邻的下层间介电层和相邻的上层间电介质层之间。 半导体材料的垂直沟道位于衬底上并沿着垂直方向延伸穿过多个层间电介质层和多个栅极图案。 垂直通道具有外侧壁，外侧壁具有多个通道凹槽，每个通道凹槽对应于多个栅极图案的栅极图案。 垂直通道具有内侧壁。 在每个栅极图案和垂直沟道之间的凹槽中存在信息存储层，其将栅极图案与垂直沟道绝缘。

公开(公告)号：US08455316B2

公开(公告)日：2013-06-04

申请号：US13325189

申请日：2011-12-14

申请人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

发明人： Yong-Hoon Son ,  Jong-Wook Lee ,  Jong-Hyuk Kang

IPC分类号： H01L21/8242 ,  H01L27/108

CPC分类号： H01L27/10852 ,  B82Y10/00 ,  H01L21/823487 ,  H01L27/10876 ,  H01L29/0673 ,  H01L29/0676 ,  H01L29/66439 ,  H01L29/66666 ,  H01L29/775 ,  H01L29/7827

摘要： A vertical semiconductor device, a DRAM device, and associated methods, the vertical semiconductor device including single crystalline active bodies vertically disposed on an upper surface of a single crystalline substrate, each of the single crystalline active bodies having a first active portion on the substrate and a second active portion on the first active portion, and the first active portion having a first width smaller than a second width of the second active portion, a gate insulating layer on a sidewall of the first active portion and the upper surface of the substrate, a gate electrode on the gate insulating layer, the gate electrode having a linear shape surrounding the active bodies, a first impurity region in the upper surface of the substrate under the active bodies, and a second impurity region in the second active portion.

摘要翻译： 垂直半导体器件，DRAM器件和相关方法，垂直半导体器件包括垂直设置在单晶衬底的上表面上的单晶有源体，每个单晶有源体在衬底上具有第一有源部分， 所述第一有源部分的第二有源部分和所述第一有源部分具有小于所述第二有源部分的第二宽度的第一宽度，所述第一有源部分的侧壁和所述衬底的上表面上的栅极绝缘层， 所述栅电极在所述栅极绝缘层上，所述栅电极具有围绕所述有源体的直线形状，所述基板的所述有源体下方的上表面中的第一杂质区域和所述第二有源部分中的第二杂质区域。

公开(公告)号：US08450176B2

公开(公告)日：2013-05-28

申请号：US12968595

申请日：2010-12-15

申请人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

发明人： Yong-Hoon Son ,  Kihyun Hwang ,  Seungjae Baik

IPC分类号： H01L21/336

CPC分类号： H01L21/28 ,  H01L27/11548 ,  H01L27/11551 ,  H01L27/11556 ,  H01L27/11575 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/792

摘要： Methods of forming nonvolatile memory devices include forming a vertical stack of nonvolatile memory cells on a substrate. This is done by forming a vertical stack of spaced-apart gate electrodes on a first sidewall of a vertical silicon active layer and treating a second sidewall of the vertical silicon active layer in order to reduce crystalline defects within the active layer and/or reduce interface trap densities therein. This treating can include exposing the second sidewall with an oxidizing species that converts a surface of the second sidewall into a silicon dioxide passivation layer. A buried insulating pattern may also be formed directly on the silicon dioxide passivation layer.

摘要翻译： 形成非易失性存储器件的方法包括在衬底上形成垂直堆叠的非易失性存储单元。 这通过在垂直硅有源层的第一侧壁上形成间隔开的栅电极的垂直堆叠来完成，并且处理垂直硅有源层的第二侧壁以便减少有源层内的晶体缺陷和/或减少界面 其中的陷阱密度。 该处理可以包括用氧化物质暴露第二侧壁，该氧化物质将第二侧壁的表面转化为二氧化硅钝化层。 也可以直接在二氧化硅钝化层上形成掩埋绝缘图案。

公开(公告)号：US08445317B2

公开(公告)日：2013-05-21

申请号：US13030454

申请日：2011-02-18

申请人： Jin Ha Jeong ,  Jung-Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

发明人： Jin Ha Jeong ,  Jung-Ho Kim ,  Kihyun Hwang ,  Yong-Hoon Son

IPC分类号： H01L21/84

CPC分类号： H01L27/11578 ,  H01L27/11582 ,  H01L29/42352 ,  H01L29/4236 ,  H01L29/66666 ,  H01L29/66833 ,  H01L29/7827 ,  H01L29/7926

摘要： Methods for fabricating a semiconductor device are provided. In the methods, first material layers and second material layers may be alternatingly and repeatedly stacked on a substrate. An opening penetrating the first material layers and the second material layers may be formed. A semiconductor solution may be formed in the opening by using a spin-on process.

摘要翻译： 提供了制造半导体器件的方法。 在这些方法中，第一材料层和第二材料层可以交替地和重复堆叠在基底上。 可以形成贯穿第一材料层和第二材料层的开口。 可以通过使用旋涂工艺在开口中形成半导体溶液。

公开(公告)号：US20130115761A1

公开(公告)日：2013-05-09

申请号：US13724632

申请日：2012-12-21

申请人： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

发明人： Jung Ho Kim ,  Sunghae Lee ,  Hanvit Yang ,  Dongwoo Kim ,  Chaeho Kim ,  Daehyun Jang ,  Ju-Eun Kim ,  Yong-Hoon Son ,  Sangryol Yang ,  Myoungbum Lee ,  Kihyun Hwang

IPC分类号： H01L21/04

CPC分类号： H01L21/04 ,  H01L27/11582 ,  H01L29/66833 ,  H01L29/7926

摘要： Methods of forming a semiconductor device are provided. The methods may include forming first and second layers that are alternately and repeatedly stacked on a substrate, and forming an opening penetrating the first and second layers. The methods may also include forming a first semiconductor pattern in the opening. The methods may additionally include forming an insulation pattern on the first semiconductor pattern. The methods may further include forming a second semiconductor pattern on the insulation pattern. The methods may also include providing dopants in the first semiconductor pattern. Moreover, the methods may include thermally treating a portion of the first semiconductor pattern to form a third semiconductor pattern.

摘要翻译： 提供了形成半导体器件的方法。 所述方法可以包括形成在衬底上交替和重复堆叠的第一和第二层，以及形成穿透第一层和第二层的开口。 所述方法还可以包括在开口中形成第一半导体图案。 所述方法还可以包括在第一半导体图案上形成绝缘图案。 所述方法还可以包括在绝缘图案上形成第二半导体图案。 所述方法还可以包括在第一半导体图案中提供掺杂剂。 此外，所述方法可以包括热处理第一半导体图案的一部分以形成第三半导体图案。

公开(公告)号：US20110298038A1

公开(公告)日：2011-12-08

申请号：US13153009

申请日：2011-06-03

申请人： Yong-Hoon SON ,  Kihyun Hwang

发明人： Yong-Hoon SON ,  Kihyun Hwang

IPC分类号： H01L29/792

CPC分类号： H01L29/7889 ,  H01L27/11578 ,  H01L27/11582 ,  H01L29/7926

摘要： Provided are a three-dimensional semiconductor memory device and manufacturing method of the three-dimensional semiconductor memory device. The three-dimensional semiconductor memory device may include a gate structure on a substrate with the gate structure including a plurality of gate electrodes. Conductive lines are disposed between the gate structure and the substrate. A horizontal semiconductor pattern is disposed between the gate structure and the conductive line. And a vertical semiconductor pattern penetrating the gate structure is connected to the horizontal semiconductor pattern.

摘要翻译： 提供三维半导体存储器件和三维半导体存储器件的制造方法。 所述三维半导体存储器件可以包括栅极结构，所述栅极结构在所述栅极结构包括多个栅电极的基板上。 导电线设置在栅极结构和衬底之间。 在栅极结构和导电线之间设置水平半导体图案。 并且穿过栅极结构的垂直半导体图案连接到水平半导体图案。

公开(公告)号：US08039350B2

公开(公告)日：2011-10-18

申请号：US12582073

申请日：2009-10-20

申请人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

发明人： Yong-Hoon Son ,  Si-Young Choi ,  Byeong-Chan Lee ,  Deok-Hyung Lee ,  In-Soo Jung

IPC分类号： H01L21/336

CPC分类号： H01L29/6659 ,  H01L29/665 ,  H01L29/66636 ,  H01L29/7833

摘要： Methods of fabricating metal-oxide-semiconductor (MOS) transistors having elevated source/drain regions are provided. The MOS transistors formed by these methods may include a gate pattern formed to cross over a predetermined region of a substrate. Recessed regions are provided in the substrate adjacent to the gate pattern. Epitaxial layers are provided on bottom surfaces of the recessed regions. High concentration impurity regions are provided in the epitaxial layers. The recessed regions may be formed using a chemical dry etching techniques.

摘要翻译： 提供了具有升高的源极/漏极区域的金属氧化物半导体（MOS）晶体管的制造方法。 通过这些方法形成的MOS晶体管可以包括形成为跨越衬底的预定区域的栅极图案。 凹陷区域设置在与栅极图案相邻的衬底中。 外凹层设置在凹陷区域的底表面上。 在外延层中设置高浓度杂质区。 凹陷区域可以使用化学干蚀刻技术形成。