公开(公告)号：US07928949B2

公开(公告)日：2011-04-19

申请号：US11274605

申请日：2005-11-15

申请人： Kyung-Wol Kim ,  Yong-Weon Jeon ,  Jong-Hoon Hong

发明人： Kyung-Wol Kim ,  Yong-Weon Jeon ,  Jong-Hoon Hong

IPC分类号： G09G3/36 ,  G09G5/00

CPC分类号： G09G3/3685 ,  G09G2310/0248 ,  G09G2310/0251 ,  G09G2310/027 ,  G09G2320/0252 ,  G09G2330/021

摘要： A source driver of a display panel includes a channel state signal generator, first switches, and second switches. The channel state signal generator generates first and second channel state signals that are each activated for a respective time period depending on adjustable state length data. The first switches are opened for uncoupling channel output signals from source lines of the display panel when the first channel state signal is activated. The second switches are closed for coupling together the source lines of the display panel for charge sharing when the second channel state signal is activated.

摘要翻译： 显示面板的源极驱动器包括通道状态信号发生器，第一开关和第二开关。 信道状态信号发生器根据可调状态长度数据生成各自针对相应时间周期激活的第一和第二信道状态信号。 当第一通道状态信号被激活时，第一开关被打开用于使来自显示面板的源极线的通道输出信号解耦。 当第二通道状态信号被激活时，第二开关闭合以将显示面板的源极线耦合在一起用于电荷共享。

公开(公告)号：US20090195266A1

公开(公告)日：2009-08-06

申请号：US12352812

申请日：2009-01-13

申请人： Yong Weon Jeon

发明人： Yong Weon Jeon

IPC分类号： H03K19/00 ,  H03K19/0175

CPC分类号： H03K3/35613 ,  G01R31/3004

摘要： A high voltage stress test circuit includes an internal data generation unit for generating internal data and inverted internal data, and a level shifter for receiving the internal data and the inverted internal data and for generating digital data and inverted digital data. In a normal mode, the internal data and the inverted internal data have logic states corresponding to input data, while the digital data and the inverted digital data have logic states corresponding to the internal data and the inverted internal data. In a high voltage stress test mode, the internal data and the inverted internal data have predetermined logic states regardless of a logic state of the input data, while the digital data and the inverted digital data have predetermined logic states regardless of logic states of the internal data and the inverted internal data.

摘要翻译： 高电压应力测试电路包括用于产生内部数据和反相内部数据的内部数据产生单元，以及用于接收内部数据和反相内部数据并用于产生数字数据和反相数字数据的电平转换器。 在正常模式下，内部数据和反转的内部数据具有与输入数据对应的逻辑状态，而数字数据和反相数字数据具有与内部数据和反转的内部数据相对应的逻辑状态。 在高压应力测试模式中，无论输入数据的逻辑状态如何，内部数据和反相内部数据都具有预定的逻辑状态，而数字数据和反相数字数据具有预定的逻辑状态，而不管内部的逻辑状态如何 数据和反向内部数据。

公开(公告)号：US07545182B2

公开(公告)日：2009-06-09

申请号：US11700117

申请日：2007-01-31

申请人： Jan-Jin Nam ,  Yong-Weon Jeon

发明人： Jan-Jin Nam ,  Yong-Weon Jeon

IPC分类号： H03K5/22

CPC分类号： H03K5/2472

摘要： A current mode comparator for a semiconductor device is disclosed. The current mode comparator may include a logic circuit coupled to a voltage sensing node, a first cascode coupled to the voltage sensing node and a first power node, and a second cascode coupled to the voltage sensing node and a second power node. The logic circuit may convert a voltage of the voltage sensing node to an output signal.

摘要翻译： 公开了一种用于半导体器件的电流模式比较器。 电流模式比较器可以包括耦合到电压感测节点的逻辑电路，耦合到电压感测节点的第一共源共栅和第一功率节点，以及耦合到电压感测节点和第二功率节点的第二共源共栅。 逻辑电路可以将电压感测节点的电压转换为输出信号。

公开(公告)号：US20080030390A1

公开(公告)日：2008-02-07

申请号：US11832095

申请日：2007-08-01

申请人： Yong-Weon JEON ,  Ji-Woon JUNG ,  Jo-Hyun KO

发明人： Yong-Weon JEON ,  Ji-Woon JUNG ,  Jo-Hyun KO

IPC分类号： H03M1/66

CPC分类号： H03M1/68 ,  H03M1/76

摘要： A digital to analog converter (DAC) converting digital data into a corresponding analog voltage is disclosed. The digital data includes upper bit data and lower bit data and the DAC includes; a first resistor circuit dividing first and second reference voltages to output a plurality of first division voltages, a first decoder selecting one of the first division voltages in response to the upper bit data, a second resistor circuit dividing third and fourth reference voltages to output a plurality of second division voltages, a second decoder selecting one of the second division voltages in response to the lower bit data, and a sample and hold circuit including a first capacitor and a second capacitor, and outputting the analog voltage in response to an output voltage from the first decoder and an output voltage from the second decoder, wherein the sample and hold circuit samples the output voltage of the first decoder during a sample mode, and adds the output voltages of the first and second decoders through the first and second capacitors to output a combined voltage during a hold mode.

摘要翻译： 公开了将数字数据转换成相应的模拟电压的数模转换器（DAC）。 数字数据包括高位数据和低位数据，DAC包括; 第一电阻器电路，分隔第一和第二参考电压以输出多个第一分压，第一解码器响应于高位数据选择第一分压电压之一;第二电阻器电路，分隔第三和第四参考电压以输出 多个第二分频电压，第二解码器响应于低位数据选择第二除法电压中的一个;以及采样保持电路，包括第一电容器和第二电容器，并且响应于输出电压输出模拟电压 来自第一解码器和来自第二解码器的输出电压，其中采样和保持电路在采样模式期间对第一解码器的输出电压进行采样，并且通过第一和第二电容器将第一和第二解码器的输出电压加到 在保持模式期间输出组合电压。

公开(公告)号：US07279985B2

公开(公告)日：2007-10-09

申请号：US11053158

申请日：2005-02-07

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： H03F1/22

CPC分类号： H03F1/223

摘要： A regulated cascode amplifier includes a main cascode amplifier and a feed-back amplifier. The main cascode amplifier has an input transistor coupled in a stack with an output transistor at an input control node. The feed-back amplifier including a plurality of transistors with gates of the transistors being coupled together to the input control node and with drains of the transistors being coupled together at a gate of the output transistor. The transistors of the feed-back amplifier are biased from connections to the main cascode amplifier for smaller chip area.

摘要翻译： 调节级联放大器包括主级联放大器和反馈放大器。 主级联放大器具有与输入控制节点处的输出晶体管堆叠的输入晶体管。 所述反馈放大器包括多个晶体管，所述晶体管的晶体管的栅极被耦合到输入控制节点，并且晶体管的漏极在输出晶体管的栅极耦合在一起。 反馈放大器的晶体管从连接到主级联放大器偏置较小的芯片面积。

公开(公告)号：US07259742B2

公开(公告)日：2007-08-21

申请号：US11302230

申请日：2005-12-14

申请人： Il-Kwon Chang ,  Yong-Weon Jeon

发明人： Il-Kwon Chang ,  Yong-Weon Jeon

IPC分类号： G09G3/36

CPC分类号： G09G3/20 ,  G09G3/3614 ,  G09G3/3685 ,  G09G2310/027 ,  G09G2310/0275 ,  G09G2310/08

摘要： A source driving circuit for a display device may include a first latch configured to store first video data corresponding to a first horizontal line and a second latch configured to store second video data corresponding to a second horizontal line following the first horizontal line. The first and second latches may alternately store video data of different horizontal lines. The source driving circuit may further include a digital-to-analog converter (DAC) configured to convert the stored first and second video data into analog signals, a first sample-and-hold circuit configured to sample and store an output signal of the DAC, a second sample-and-hold circuit configured to sample and store an output signal of the first sample-and-hold circuit, and an output switch configured to provide an output signal of the second sample-and-hold circuits to the display panel.

摘要翻译： 用于显示装置的源极驱动电路可以包括配置为存储对应于第一水平线的第一视频数据的第一锁存器和被配置为存储对应于第一水平线之后的第二水平线的第二视频数据的第二锁存器。 第一和第二锁存器可以交替地存储不同水平线的视频数据。 源极驱动电路还可以包括被配置为将所存储的第一和第二视频数据转换为模拟信号的数模转换器（DAC），第一采样保持电路被配置为对DAC的输出信号进行采样和存储 配置为采样并存储第一采样保持电路的输出信号的第二采样保持电路，以及配置成将第二采样保持电路的输出信号提供给显示面板的输出开关 。

公开(公告)号：US20070176610A1

公开(公告)日：2007-08-02

申请号：US11700046

申请日：2007-01-31

申请人： Jan-Jin Nam ,  Yong-Weon Jeon

发明人： Jan-Jin Nam ,  Yong-Weon Jeon

IPC分类号： G01R27/08

CPC分类号： G01R31/2884

摘要： Provided is a current-mode semiconductor integrated circuit device that operates in a voltage mode during a test mode. The current-mode semiconductor integrated circuit device includes a first transmitting converter, a first receiving converter, a second transmitting converter, and a second receiving converter. During the test mode, one of a first signal path and a second signal path is selected according to the location of the chip. In the first signal path, the first transmitting converter, the first receiving converter, and the second transmitting converter operate. In the second signal path, the second transmitting converter, the second receiving converter, and the first transmitting converter operate. Each of the first and second transmitting converters receives a test voltage signal and converts it into a current signal. Each of the first and second receiving converters generates a reference voltage signal, compares it with the test voltage signal, and outputs the comparing result. Accordingly, it is possible to test the current-mode operation of a semiconductor chip with an external tester operating in a current mode by including an interface circuit capable of performing voltage-to-current conversion into the semiconductor chip.

摘要翻译： 提供了在测试模式期间以电压模式操作的电流模式半导体集成电路器件。 电流模式半导体集成电路装置包括第一发送转换器，第一接收转换器，第二发送转换器和第二接收转换器。 在测试模式期间，根据芯片的位置来选择第一信号路径和第二信号路径之一。 在第一信号路径中，第一发送转换器，第一接收转换器和第二发送转换器工作。 在第二信号路径中，第二发送转换器，第二接收转换器和第一发送转换器工作。 第一和第二发送转换器中的每一个接收测试电压信号并将其转换为电流信号。 第一和第二接收转换器中的每一个产生参考电压信号，将其与测试电压信号进行比较，并输出比较结果。 因此，通过包括能够对半导体芯片进行电压 - 电流转换的接口电路，可以利用以电流模式工作的外部测试器来测试半导体芯片的电流模式操作。

公开(公告)号：US06927609B2

公开(公告)日：2005-08-09

申请号：US10776910

申请日：2004-02-11

申请人： Il-kwon Chang ,  Yong-weon Jeon ,  Ji-woon Jung

发明人： Il-kwon Chang ,  Yong-weon Jeon ,  Ji-woon Jung

IPC分类号： G05F3/26 ,  H03K19/0185 ,  H04L25/02 ,  H03K3/00

CPC分类号： H04L25/0294 ,  G09G2310/0275 ,  H03K19/018571

摘要： A current-mode data receiving device with sufficient fidelity for a display system. The receiving device includes: a current mirror, where an input current signal and a feedback current signal is received at a first terminal thereof and an output current signal with a current magnitude proportional to (e.g., equal to) the sum of the magnitudes of the input current signal and of the feedback current signal is output through a second terminal thereof; and a feedback unit that uses the magnitude of the output current signal as feedback to determined the magnitude and direction of the feedback current to the first terminal, and causes a decreases in the magnitude of the output current signal by a predetermined amount if the output current signal is at a high level, and increases the current magnitude of the output current signal by the predetermined amount if the magnitude of the output current signal is at a low level. Therefore, it is possible to correctly receive even a high-frequency signal and an irregular signal.

摘要翻译： 一种具有足够保真度的显示系统的电流模式数据接收装置。 接收装置包括：电流镜，其中在其第一端处接收输入电流信号和反馈电流信号，并且输出电流信号的电流大小与（例如，等于）等于 输入电流信号和反馈电流信号通过其第二端输出; 以及反馈单元，其使用输出电流信号的幅度作为反馈来确定到第一端子的反馈电流的大小和方向，并且如果输出电流导致输出电流信号的幅度减小预定量，则反馈单元 信号处于高电平，并且如果输出电流信号的幅度处于低电平，则将输出电流信号的电流幅度增加预定量。 因此，可以正确地接收高频信号和不规则信号。

公开(公告)号：US20050152189A1

公开(公告)日：2005-07-14

申请号：US11035596

申请日：2005-01-13

申请人： Kyung-Wol Kim ,  Yong-Weon Jeon

发明人： Kyung-Wol Kim ,  Yong-Weon Jeon

IPC分类号： G02F1/133 ,  G09G3/20 ,  G09G3/36 ,  G09G5/00 ,  G11C16/04

CPC分类号： G09G3/3685 ,  G09G2320/02

摘要： A display device includes source drivers connected to a timing controller in a serial cascade. First through third buses are connected between the timing controller and a first source driver of source drivers. In a first period of time, a clock signal is transmitted via the first bus, a first operation control signal is transmitted via the second bus, a second operation control signal is transmitted via the third bus, and a polarity control signal is transmitted via the third bus. In a second period of time, the clock signal is transmitted via the first bus, the first operation control signal is transmitted via the second bus, and the second operation control signal is transmitted via the third bus. Source drivers generate a data initiation signal and a load signal using a combination of the logic levels of the operation control signals during each period.

摘要翻译： 显示装置包括以串联级联连接到定时控制器的源极驱动器。 第一至第三总线连接在时序控制器和源驱动器的第一源驱动器之间。 在第一时间段中，通过第一总线发送时钟信号，经由第二总线发送第一操作控制信号，经由第三总线发送第二操作控制信号，经由该第二总线发送极性控制信号 第三班车。 在第二时间段中，经由第一总线发送时钟信号，经由第二总线发送第一操作控制信号，经由第三总线发送第二操作控制信号。 源驱动器在每个周期内使用操作控制信号的逻辑电平的组合产生数据启动信号和负载信号。

公开(公告)号：US5907520A

公开(公告)日：1999-05-25

申请号：US702112

申请日：1996-08-23

申请人： Oh-Sang Yoon ,  Yong-Weon Jeon

发明人： Oh-Sang Yoon ,  Yong-Weon Jeon

IPC分类号： G11C11/41 ,  G06F13/14 ,  G11C7/12 ,  G11C8/18 ,  G11C8/00

CPC分类号： G11C7/12 ,  G11C8/18

摘要： A circuit for generating equalization pulses for a memory device is disclosed, which prevents formation of a short circuit between a Vdd potential and a Vss potential when two address transition signals are successively generated, and which generates the equalization pulses by using address transition pulses and by reducing the access time of the memory device. The equalization pulse generating circuit includes a NAND circuit section for outputting a NAND logic of address transition signals under address transitions to an equalization pulse generating node, a delay circuit section for delaying an output of the equalization pulse generating node for a certain period of time, so as to generate at least one delayed output signal, and a maintaining circuit section for logically processing the delayed output signal of the delay circuit section and the NAND logic output of the NAND circuit section, so as to maintain the state of the equalization pulse generating node in the same state for a certain period of time.

摘要翻译： 公开了一种用于产生用于存储器件的均衡脉冲的电路，其防止当连续产生两个地址转换信号时在Vdd电位和Vss电位之间形成短路，并且通过使用地址转换脉冲和 减少存储设备的访问时间。 均衡脉冲发生电路包括：NAND电路部分，用于将地址转换下的地址转换信号的与非逻辑逻辑输出到均衡脉冲产生节点;延迟电路部分，用于将均衡脉冲产生节点的输出延迟一段时间， 以产生至少一个延迟的输出信号;以及维持电路部分，用于对延迟电路部分的延迟输出信号和NAND电路部分的NAND逻辑输出进行逻辑处理，以保持产生均衡脉冲的状态 节点处于相同状态一段时间。