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公开(公告)号：US20100061132A1
公开(公告)日：2010-03-11
申请号：US12516690
申请日：2006-12-07
CPC分类号： H01L45/144 , G11C13/0004 , G11C13/0069 , G11C2213/75 , H01L27/2436 , H01L27/2463 , H01L27/2472 , H01L45/06 , H01L45/1233
摘要： In a semiconductor storage device such as a phase change memory, a technique which can realize high integration is provided. The semiconductor storage device includes a phase change thin film 101 having two stable phases of a crystal state with low electric resistance and an amorphous state with high electric resistance, upper plug electrodes 102 and 103 provided on one side of the phase change thin film 101, a lower electrode 104 provided on the other side of the phase change thin film 101, a selecting transistor 114 whose drain/source terminals are connected to the upper plug electrode 102 and the lower electrode 104, and a selecting transistor 115 whose drain/source terminals are connected to the upper plug electrode 103 and the lower electrode 104, and a first memory cell is configured with the selecting transistor 114 and a phase change region 111 in the phase change thin film 101 sandwiched between the upper plug electrode 102 and the lower electrode 104, and a second memory cell is configured with the selecting transistor 115 and a phase change region 112 in the phase change thin film 101 sandwiched between the upper plug electrode 103 and the lower electrode 104.
摘要翻译： 在诸如相变存储器的半导体存储装置中，提供了可以实现高集成度的技术。 半导体存储装置包括：具有低电阻的晶体状态的两个稳定相和具有高电阻的非晶态的相变薄膜101，设置在相变薄膜101一侧的上部插塞电极102和103， 设置在相变薄膜101的另一侧的下部电极104，漏极/源极端子连接到上部插塞电极102和下部电极104的选择晶体管114，以及选择晶体管115，其漏极/源极端子 连接到上插头电极103和下电极104，并且第一存储单元配置有夹在上插头电极102和下电极之间的相变薄膜101中的选择晶体管114和相变区域111 104，并且第二存储单元配置有夹在b中的相变薄膜101中的选择晶体管115和相变区域112 在上塞电极103和下电极104之间。
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公开(公告)号：US20090052231A1
公开(公告)日：2009-02-26
申请号：US12162702
申请日：2006-02-02
CPC分类号： G11C13/0069 , G11C13/0004 , G11C2013/0073 , G11C2013/0078 , G11C2213/79 , H01L27/24
摘要： A semiconductor device capable of high-speed read and has a high data-retention characteristic is provided. In a semiconductor device including a memory array having a plurality of memory cells provided at intersecting points of a plurality of word lines and a plurality of bit lines, where each memory cell includes an information memory section and a select element, when information is programmed by a first pulse (reset operation) for programming information flowing in the bit line and a second pulse (set operation) different from the first pulse and information is read by a third pulse (read operation), current directions of the second pulse and the third pulse are opposite to each other.
摘要翻译： 提供了一种能够高速读取并具有高数据保持特性的半导体器件。 在包括具有设置在多个字线和多个位线的交叉点处的多个存储单元的存储器阵列的半导体器件中，其中每个存储单元包括信息存储器部分和选择元件，当信息由 用于编程在位线中流动的信息的第一脉冲（复位操作）和与第一脉冲和信息不同的第二脉冲（置位操作）被第三脉冲（读操作）读取，第二脉冲和第三脉冲 脉冲彼此相反。
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3.发明授权Semiconductor storage device manufacturing method which forms a hydrogen diffusion inhibiting layer 失效形成氢扩散抑制层的半导体存储装置的制造方法公开(公告)号：US06818523B2
公开(公告)日：2004-11-16
申请号：US10602644
申请日：2003-06-25
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
IPC分类号： Y01L2120
摘要： A method for forming a semiconductor storage device includes steps of forming a memory cell transistor, forming a first plug connected to the memory cell transistor, forming a second plug of a hydrogen diffusion inhibiting layer, forming capacitor electrodes and a capacitor insulator between the capacitor electrodes and forming a hydrogen adsorption inhibiting layer.
摘要翻译： 一种形成半导体存储装置的方法，包括：形成存储单元晶体管，形成连接到存储单元晶体管的第一插头，形成氢扩散抑制层的第二插头，在电容器电极之间形成电容器电极和电容器绝缘体 并形成氢吸附抑制层。
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4.发明授权III-V single crystal as well as method of producing the same, and semiconductor device utilizing the III-V single crystal 失效III-V单晶及其制造方法，以及利用III-V单晶的半导体器件公开(公告)号：US06815741B2
公开(公告)日：2004-11-09
申请号：US10624612
申请日：2003-07-23
申请人： Yoshihisa Fujisaki , Yukio Takano , Tsutomu Ishiba
发明人： Yoshihisa Fujisaki , Yukio Takano , Tsutomu Ishiba
IPC分类号： H01L2980
CPC分类号： H01L29/32 , C30B15/00 , C30B29/42 , H01L29/207 , H01L2924/0002 , H01L2924/00
摘要： By exploiting an intense correlation exhibited between the distribution of lattice distortions in a wafer and the distribution of the threshold voltages of field effect transistors, the distribution of the lattice distortions in the wafer is reduced, thereby to mitigate the distribution of the characteristics of the semiconductor elements in the wafer. The difference between the maximum value and minimum value of the lattice distortions of a III-V single crystal at a normal temperature is set to at most 4×10−5, and the density of Si atoms contained in the III-V single crystal is set to at most 1×1016 cm−3, whereby the characteristics of semiconductor elements whose parent material is the III-V single crystal can be made uniform.
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公开(公告)号：US06396092B1
公开(公告)日：2002-05-28
申请号：US09381396
申请日：1999-09-20
IPC分类号： H01L2906
摘要： A semiconductor device includes a capacitor having a lower electrode (102), a high-dielectric-constant or ferroelectric thin film (103), and an upper electrode (104) which are subsequently stacked. An impurity having an action of suppressing the catalytic activity of a metal or a conductive oxide constituting the electrode is added to the upper electrode (104). The addition of the impurity is effective to prevent inconveniences such as a reduction in capacitance, an insulation failure, and the peeling of the electrode due to hydrogen heat-treatment performed after formation of the upper electrode (104), and to improve the long-term reliability.
摘要翻译： 半导体器件包括随后堆叠的具有下电极（102），高介电常数或铁电薄膜（103）和上电极（104）的电容器。 具有抑制构成电极的金属或导电氧化物的催化活性的作用的杂质被添加到上电极（104）。 杂质的添加对于防止在形成上电极（104）之后进行的氢热处理等电容的减少，绝缘失效以及电极的剥离等不良情况是有效的， 长期可靠性。
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公开(公告)号：US06380574B1
公开(公告)日：2002-04-30
申请号：US09674392
申请日：2000-10-31
IPC分类号： H01L2976
CPC分类号： H01L21/7687 , H01L27/10814 , H01L27/10817 , H01L27/10852 , H01L27/10855 , H01L27/10894 , H01L28/75
摘要： A diffusion preventive layer extending between the bottom surface of a lower electrode and an interconnection connecting the lower electrode to one of the diffusion layers of a switching transistor is self-aligned. As a result, no side trench is produced since a hole pattern is formed by using a dummy film, and even if a contact plug of a memory section is misaligned with the diffusion preventive layer, the contact plug is out of direct contact with a dielectric film having a high permittivity. Hence, a highly reliable device can be obtained.
摘要翻译： 在下电极的底表面和将下电极连接到开关晶体管的一个扩散层的布线之间延伸的扩散防止层是自对准的。 结果，由于通过使用虚拟膜形成孔图案，所以不产生侧沟槽，并且即使存储部分的接触插塞与扩散防止层不对准，接触插塞不与电介质直接接触 具有高介电常数的薄膜。 因此，可以获得高度可靠的装置。
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公开(公告)号：US6144052A
公开(公告)日：2000-11-07
申请号：US142011
申请日：1998-08-31
申请人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
发明人： Keiko Kushida , Masahiko Hiratani , Kazuyoshi Torii , Shinichiro Takatani , Hiroshi Miki , Yuuichi Matsui , Yoshihisa Fujisaki
IPC分类号： H01L21/02 , H01L21/8242 , H01L27/108 , H01L29/72
CPC分类号： H01L27/10852 , H01L28/55 , H01L28/60 , H01L27/10814 , H01L27/10888
摘要： An oriented polycrystal silicon film or an amorphous silicon film 52 is disposed on the whole area beneath a conductive diffusion barrier 61 under a lower electrode of a ferroelectric capacitor. As a result, the conductive diffusion barrier, the lower electrode and the capacitor ferroelectric film become oriented films; therefore, it is possible to reduce the signal variation in capacitors even in minute semiconductor devices, and obtain a highly reliable semiconductor device.
摘要翻译： PCT No.PCT / JP96 / 00579 Sec。 371日期1998年8月31日 102（e）1998年8月31日PCT 1996年3月8日PCT公布。 公开号WO97 / 33316 PCT 日期1997年9月12日在铁电电容器的下电极下方的导电性扩散阻挡层61的下方的整个区域上设置取向多晶硅膜或非晶硅膜52。 结果，导电扩散阻挡层，下电极和电容器铁电体膜成为取向膜; 因此，即使在微小的半导体器件中也可以减小电容器的信号变化，并获得高可靠性的半导体器件。
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公开(公告)号：US20090014708A1
公开(公告)日：2009-01-15
申请号：US12169818
申请日：2008-07-09
申请人： Yoshitaka SASAGO , Motoyasu Terao , Norikatsu Takaura , Yoshihisa Fujisaki , Tomoyuki Kodama , Nobuyuki Arasawa
发明人： Yoshitaka SASAGO , Motoyasu Terao , Norikatsu Takaura , Yoshihisa Fujisaki , Tomoyuki Kodama , Nobuyuki Arasawa
IPC分类号： H01L45/00
CPC分类号： H01L45/1206 , G06N3/063 , G11C13/0011 , H01L45/085 , H01L45/142 , H01L45/146 , H01L45/1675
摘要： A nonvolatile, sophisticated semiconductor device with a small surface area and a simple structure capable of switching connections between three or more electrodes. In a semiconductor device at least one of the electrodes contains atoms such as copper or silver in the solid electrolyte capable of easily moving within the solid electrolyte, and those electrodes face each other and applying a voltage switches the voltage on and off by generating or annihilating the conductive path between the electrodes. Moreover applying a voltage to a separate third electrode can annihilate the conductive path formed between two electrodes without applying a voltage to the two electrode joined by the conductive path.
摘要翻译： 具有小表面积的非易失性，复杂的半导体器件和能够切换三个或更多个电极之间的连接的简单结构。 在半导体器件中，电极中的至少一个在固体电解质中含有诸如铜或银之类的原子，能够容易地在固体电解质内移动，并且这些电极彼此面对并且施加电压通过产生或消除电压来开启和关闭电压 电极之间的导电路径。 此外，向单独的第三电极施加电压可以消除在两个电极之间形成的导电路径，而不向由导电路径连接的两个电极施加电压。
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9.发明申请Method of fabricating a semiconductor device including a reaction barrier film, a diffusion barrier film and a ferroelectric film 审中-公开制造包括反应阻挡膜，扩散阻挡膜和铁电体膜的半导体器件的方法公开(公告)号：US20050074936A1
公开(公告)日：2005-04-07
申请号：US10968077
申请日：2004-10-20
IPC分类号： H01L27/10 , H01L21/02 , H01L21/285 , H01L21/8242 , H01L21/8246 , H01L27/105 , H01L27/108 , H01L21/00
CPC分类号： H01L28/56 , H01L21/28568 , H01L27/10852 , H01L27/10855 , H01L28/55 , H01L28/75
摘要： A method of fabricating a semiconductor device, is provided including forming an insulating film having an opening portion on a substrate having a transistor, filling a conductive film in the opening portion, forming a reaction barrier film functioning to prevent a reaction on the insulating film, and forming a diffusion barrier film on the conductive film. Next a first electrode is formed on the diffusion barrier film, a ferroelectric film, including at least one element of the group consisting of lead, barium and bismuth is formed on the first electrode after the step of forming the reaction barrier film, and a second electrode is formed on the ferroelectric film.
摘要翻译： 提供一种制造半导体器件的方法，包括：在具有晶体管的衬底上形成具有开口部分的绝缘膜，在开口部分填充导电膜，形成用于防止对绝缘膜发生反应的反应阻挡膜， 并在导电膜上形成扩散阻挡膜。 接下来，在扩散阻挡膜上形成第一电极，在形成反应阻挡膜的步骤之后，在第一电极上形成包括由铅，钡和铋组成的组中的至少一种元素的铁电体膜，第二电极形成第二电极 电极形成在铁电体膜上。
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10.发明申请公开(公告)号：US20050051821A1
公开(公告)日：2005-03-10
申请号：US10920344
申请日：2004-08-18
申请人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
发明人： Hiroshi Miki , Keiko Kushida , Yasuhiro Shimamoto , Shinichiro Takatani , Yoshihisa Fujisaki , Hiromi Nakai
摘要： The upper electrode of a capacitor is constituted of laminated films which act to prevent hydrogen atoms from reaching the capacitor electrodes and degrading performance. In one example, a four layer upper electrode respectively acts as a Schottky barrier layer, a hydrogen diffusion preventing layer, a reaction preventing layer, and an adsorption inhibiting layer. Therefore, the occurrence of a capacitance drop, imperfect insulation, and electrode peeling in the semiconductor device due to a reducing atmosphere can be prevented. In addition, the long-term reliability of the device can be improved.
摘要翻译： 电容器的上电极由层叠膜构成，其用于防止氢原子到达电容器电极并降低性能。 在一个示例中，四层上电极分别用作肖特基势垒层，氢扩散防止层，反应防止层和吸附抑制层。 因此，可以防止由于还原气氛导致半导体器件中的电容下降，绝缘不良和电极剥离的发生。 另外，可以提高装置的长期可靠性。
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