公开(公告)号：US08013442B2

公开(公告)日：2011-09-06

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8.形成在焊盘电极3上的金属层9具有形成的多个凹部10至13 另外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用这种结构，金属反应区域用作焊盘电极3上的电流路径。因此，焊盘电极3上的电阻值减小。

公开(公告)号：US20080237853A1

公开(公告)日：2008-10-02

申请号：US12056751

申请日：2008-03-27

申请人： Yoshimasa AMATATSU ,  Minoru AKAISHI ,  Satoshi ONAI ,  Katsuya OKABE ,  Yoshiaki SANO ,  Akira YAMANE

发明人： Yoshimasa AMATATSU ,  Minoru AKAISHI ,  Satoshi ONAI ,  Katsuya OKABE ,  Yoshiaki SANO ,  Akira YAMANE

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/05 ,  H01L23/293 ,  H01L24/03 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/03462 ,  H01L2224/0347 ,  H01L2224/0401 ,  H01L2224/05014 ,  H01L2224/05022 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05647 ,  H01L2224/13007 ,  H01L2224/13022 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2924/00013 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01018 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/13099 ,  H01L2224/13599 ,  H01L2224/05599 ,  H01L2224/05099 ,  H01L2224/29099 ,  H01L2224/29599 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a resistance value above a pad electrode is difficult because of an oxide film formed on a surface of the pad electrode. In a semiconductor device of this invention, an oxidation preventing metal layer is formed on a pad electrode, and the oxidation preventing metal layer is exposed at an opening region formed in a spin coat resin film at a portion above the pad electrode. In addition, a plating metal layer and a copper plated layer are formed on the oxidation preventing metal layer. With this structure, the resistance value above the pad electrode is reduced because the top surface of the pad electrode is difficult to oxidize, and the oxidation preventing metal layer having considerably smaller sheet resistivity than an oxidation film serves as part of a current path.

摘要翻译： 常规的半导体器件具有由于在焊盘电极的表面上形成氧化膜而难以降低焊盘电极之上的电阻值的问题。 在本发明的半导体器件中，在焊盘电极上形成氧化防止金属层，并且在氧化防止金属层在形成于旋转涂布树脂膜的开口区域的焊盘电极上方露出。 此外，在氧化防止金属层上形成电镀金属层和镀铜层。 利用这种结构，焊盘电极上方的电阻值降低，因为焊盘电极的顶表面难以氧化，并且具有比氧化膜小的电阻率的防氧化金属层用作电流路径的一部分。

公开(公告)号：US20110165765A1

公开(公告)日：2011-07-07

申请号：US13050345

申请日：2011-03-17

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L21/265

CPC分类号： H01L29/7322 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735

摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

摘要翻译： 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。 每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。 通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。 该结构允许减小隔离区域的形成区域。

公开(公告)号：US07791171B2

公开(公告)日：2010-09-07

申请号：US12026593

申请日：2008-02-06

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L27/082 ,  H01L27/102 ,  H01L29/70 ,  H01L31/11

CPC分类号： H01L29/7322 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/66272

摘要： In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

摘要翻译： 在根据本发明的半导体器件中，在P型衬底上形成两个外延层。 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个岛。 通过将第一和第二P型掩埋层与P型扩散层连接而形成隔离区。 通过在第一P型掩埋层和P型扩散层之间设置第二P型掩埋层，第一P型掩埋层的横向扩散宽度减小。 通过使用该结构，隔离区域的形成区域的尺寸减小。

公开(公告)号：US20080258301A1

公开(公告)日：2008-10-23

申请号：US12081487

申请日：2008-04-16

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L21/76816 ,  H01L21/32051 ,  H01L21/76838 ,  H01L21/76843 ,  H01L21/7685 ,  H01L21/76886 ,  H01L23/5226 ,  H01L23/53223 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/02166 ,  H01L2224/0345 ,  H01L2224/0346 ,  H01L2224/03462 ,  H01L2224/0401 ,  H01L2224/05008 ,  H01L2224/05096 ,  H01L2224/05147 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05548 ,  H01L2224/05554 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/11462 ,  H01L2224/1148 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13144 ,  H01L2224/13147 ,  H01L2224/16 ,  H01L2924/0002 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/0105 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2224/05552

摘要： A conventional semiconductor device has a problem that reduction of a connection resistance value between wiring layers is difficult because of an oxide film formed between the wiring layers. In a semiconductor device of this invention, a first metal layer is embeded in opening regions which connect a first wiring layer and a second wiring layer and an opening is formed in a spin coated resin film formed on the first metal layer. In the opening, a Cr layer forming a plating metal layer and a Cu plated layer are connected to each other. With this structure, the spaces among crystal grains in portions in the Cr layer on the first metal layer are wide, which causes the portions to be coarse. In the coarse portions in the Cr layer, an alloy layer formed of the second metal layer and the Cu plated layer is formed, and thus, the connection resistance value is reduced.

摘要翻译： 常规的半导体器件具有由于在布线层之间形成氧化膜而导致布线层之间的连接电阻值的降低困难的问题。 在本发明的半导体装置中，第一金属层被嵌入在连接第一布线层和第二布线层的开放区域中，并且在形成在第一金属层上的旋涂树脂膜中形成开口。 在开口中，形成镀覆金属层的Cr层和Cu镀层彼此连接。 利用这种结构，第一金属层上的Cr层中的部分中的晶粒之间的空间很宽，这使得这些部分变粗。 在Cr层的粗糙部分中，形成由第二金属层和Cu镀层形成的合金层，从而降低连接电阻值。

公开(公告)号：US08377808B2

公开(公告)日：2013-02-19

申请号：US13050345

申请日：2011-03-17

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L21/425

CPC分类号： H01L29/7322 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735

摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

摘要翻译： 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。 每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。 通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。 该结构允许减小隔离区域的形成区域。

公开(公告)号：US07910449B2

公开(公告)日：2011-03-22

申请号：US12836221

申请日：2010-07-14

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L21/331

CPC分类号： H01L29/7322 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/66272

摘要： In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

摘要翻译： 在根据本发明的半导体器件中，在P型衬底上形成两个外延层。 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个岛。 通过将第一和第二P型掩埋层与P型扩散层连接而形成隔离区。 通过在第一P型掩埋层和P型扩散层之间设置第二P型掩埋层，第一P型掩埋层的横向扩散宽度减小。 通过使用该结构，隔离区域的形成区域的尺寸减小。

公开(公告)号：US20100279482A1

公开(公告)日：2010-11-04

申请号：US12836221

申请日：2010-07-14

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L21/331

CPC分类号： H01L29/7322 ,  H01L21/761 ,  H01L21/823481 ,  H01L21/8249 ,  H01L27/0623 ,  H01L29/0821 ,  H01L29/66272

摘要： In a semiconductor device according to the present invention, two epitaxial layers are formed on a P type substrate. In the substrate and the epitaxial layers, isolation regions are formed to divide the substrate and the epitaxial layers into a plurality of islands. Each of the isolation regions is formed by connecting first and second P type buried layers with a P type diffusion layer. By disposing the second P type buried layer between the first P type buried layer and the P type diffusion layer, a lateral diffusion width of the first P type buried layer is reduced. By use of this structure, a formation region of the isolation region is reduced in size.

摘要翻译： 在根据本发明的半导体器件中，在P型衬底上形成两个外延层。 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个岛。 通过将第一和第二P型掩埋层与P型扩散层连接而形成隔离区。 通过在第一P型掩埋层和P型扩散层之间设置第二P型掩埋层，第一P型掩埋层的横向扩散宽度减小。 通过使用该结构，隔离区域的形成区域的尺寸减小。

公开(公告)号：US20080230899A1

公开(公告)日：2008-09-25

申请号：US12053168

申请日：2008-03-21

申请人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

发明人： Yoshimasa Amatatsu ,  Minoru Akaishi ,  Satoshi Onai ,  Katsuya Okabe ,  Yoshiaki Sano ,  Akira Yamane

IPC分类号： H01L23/48 ,  H01L21/44

CPC分类号： H01L24/11 ,  H01L24/05 ,  H01L24/13 ,  H01L2224/0401 ,  H01L2224/05018 ,  H01L2224/05022 ,  H01L2224/05085 ,  H01L2224/05559 ,  H01L2224/05567 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01074 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/014 ,  H01L2924/3025

摘要： In a semiconductor device according to the present invention, a plurality of opening regions 5 to 8 are formed in an insulating film on a pad electrode 3. A metal layer 9 formed on the pad electrode 3 has a plurality of concave portions 10 to 13 formed therein by covering the opening regions 5 to 8. Moreover, in a peripheral portion at a bottom of each of the concave portions 10 to 13 in the metal layer 9, the metal layer 9 and a Cu plating layer 19 react with each other. By use of this structure, the metal reaction area serves as a current path on the pad electrode 3. Thus, a resistance value on the pad electrode 3 is reduced.

摘要翻译： 在根据本发明的半导体器件中，在焊盘电极3上的绝缘膜中形成多个开口区域5至8。 形成在焊盘电极3上的金属层9通过覆盖开口区域5〜8而形成有多个凹部10〜13。 此外，在金属层9的各凹部10〜13的底部的周边部分中，金属层9和Cu镀层19相互反应。 通过使用该结构，金属反应区域作为焊盘电极3上的电流路径。 因此，焊盘电极3上的电阻值降低。

公开(公告)号：US20080150083A1

公开(公告)日：2008-06-26

申请号：US11961516

申请日：2007-12-20

申请人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

发明人： Mitsuru Soma ,  Hirotsugu Hata ,  Yoshimasa Amatatsu

IPC分类号： H01L21/331 ,  H01L29/735

CPC分类号： H01L29/7322 ,  H01L29/6625 ,  H01L29/66272 ,  H01L29/735

摘要： In the substrate and the epitaxial layer, isolation regions are formed to divide the substrate and the epitaxial layer into a plurality of element formation regions. Each of the isolation regions is formed by connecting first and second P type buried diffusion layers with a P type diffusion layer. By disposing the second P type buried diffusion layer between the first P type buried diffusion layer and the P type diffusion layer, a lateral diffusion width of the first P type buried diffusion layer is reduced. This structure allows a formation region of the isolation region to be reduced in size.

摘要翻译： 在衬底和外延层中，形成隔离区以将衬底和外延层分成多个元件形成区域。 每个隔离区域通过将第一和第二P型掩埋扩散层与P型扩散层连接而形成。 通过在第一P型埋入扩散层和P型扩散层之间设置第二P型埋入扩散层，第一P型埋入扩散层的横向扩散宽度减小。 该结构允许减小隔离区域的形成区域。